12-Bit, 370 MSPS/500 MSPS,
1.8 V Analog-to-Digital Converter
AD9434
FEATURES
SNR = 65 dBFS at f
IN
up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at f
IN
up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 78 dBc at f
IN
up to 250 MHz at 500 MSPS (−1.0 dBFS)
Integrated input buffer
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±0.6 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
690 mW at 500 MSPS—LVDS SDR mode
660 mW at 500 MSPS—LVDS DDR mode
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
FUNCTIONAL BLOCK DIAGRAM
VREF
PWDN
AGND
AVDD
REFERENCE
CML
VIN+
VIN–
TRACK-AND-HOLD
ADC
CORE
CLK+
CLK–
CLOCK
MANAGEMENT
12
AD9434
DRVDD
DRGND
OUTPUT 12
STAGING
LVDS
D11± TO D0±
OR+
OR–
SERIAL PORT
DCO+
09383-001
DCO–
SCLK/DFS
SDIO
CSB
Figure 1.
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
Fabricated on an advanced BiCMOS process, the AD9434 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C). This part is protected
under a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
High Performance.
Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.
Low Power.
Consumes only 660 mW at 500 MSPS.
Ease of Use.
LVDS output data and output clock signal allow interface
to FPGA technology. The on-chip reference and sample-
and-hold provide flexibility in system design. Use of a
single 1.8 V supply simplifies system power supply design.
Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
The AD9434 is pin compatible with the
and can
be substituted in many applications with minimal design
changes.
GENERAL DESCRIPTION
The
is a 12-bit monolithic sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a sample-and-hold and voltage
reference, are included on the chip to provide a complete signal
conversion solution. The VREF pin can be used to monitor the
internal reference or provide an external voltage reference
(external reference mode must be enabled through the SPI
port).
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is
available for proper output data timing.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
4.
5.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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