AD9764
AVDD
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
REFLO
R
FB
1.2V
OUT1
V
DD
V
REF
0.1V TO 1.2V
+1.2V REF
50pF
REFIO
FS ADJ
AGND
R
SET
DB7–DB0
I
REF
=
V
REF
/R
SET
CURRENT
SOURCE
ARRAY
COMP1
AVDD
AD7524
AD1580
OUT2
AD9764
Figure 25. Single-Supply Gain Control Circuit
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and I
REF
is
varied by an external voltage, V
GC
, applied to R
SET
via an ampli-
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
GC
, is
referenced to ACOM and should not exceed 1.2 V. The value of
R
SET
is such that I
REFMAX
and I
REFMIN
do not exceed 62.5
µA
and 625
µA,
respectively. The associated equations in Figure 26
can be used to determine the value of R
SET
.
OPTIONAL
BANDLIMITING
CAPACITOR
AVDD
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
I
OUTA
and I
OUTB
, which may be configured for single-end
or differential operation. I
OUTA
and I
OUTB
can be converted into
complementary single-ended voltage outputs, V
OUTA
and
V
OUTB
, via a load resistor, R
LOAD
, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, V
DIFF
, existing between V
OUTA
and V
OUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of I
OUTA
and I
OUTB
is determined
by the equivalent parallel combination of the PMOS switches
and is typically 100 kΩ in parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., V
OUTA
and V
OUTB
) and, to
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, I
OUTFS
. Although the output impedance’s signal depen-
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
REFLO
+1.2V REF
50pF
REFIO
1 F
R
SET
I
REF
COMP1 AVDD
FS ADJ
CURRENT
SOURCE
ARRAY
AD9764
I
REF
= (1.2–V
GC
)/R
SET
V
GC
WITH V
GC
< V
REFIO
AND 62.5 A
I
REF
625A
Figure 26. Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
EXTERNAL
CONTROL AMPLIFIER
V
REF
INPUT
REFLO
+1.2V REF
REFIO
FS ADJ
R
SET
50pF
CURRENT
SOURCE
ARRAY
COMP1 AVDD
AVDD
AD9764
AVDD
I
OUTA
R
LOAD
I
OUTB
R
LOAD
Figure 28. Equivalent Analog Output Circuit
AD9764
Figure 27. Configuring an External Reference Control
Amplifier
I
OUTA
and I
OUTB
also have a negative and positive voltage compli-
ance range. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9764. The posi-
tive output compliance range is slightly dependent on the full-
scale output current, I
OUTFS
. It degrades slightly from its nominal
REV. B
–11–
AD [ ANALOG DEVICES ]
