AD9816
ANALOG
INPUTS
PIXEL n (R, G, B)
PIXEL (n+1)
PIXEL (n+2)
PIXEL (n+m)
t
AD
t
AD
t
C1
t
C2C1
t
C1C2
t
C2
t
C2AD
t
OD
B(n–2)
R(n–1)
G(n–1)
B(n–1)
R(n)
G(n)
B(n)
R(n+1)
t
CRA
CDSCLK1
CDSCLK2
t
ADCLK
ADCCLK
OUTPUT
DATA
D11:D0
PGAOUT_T
t
ADC2
t
ADCLK
R(n–2)
G(n–2)
G(n–1)
B(n–1)
R(n)
G(n)
B(n)
R(n+1)
G(n+1)
B(n+1)
R(n+2)
PGAOUT_C
Figure 1. 3-Channel CDS Mode Timing
PIXEL n (R, G, B)
PIXEL (n+1)
PIXEL (n+2)
PIXEL (n+m)
ANALOG
INPUTS
t
AD
t
C2
CDSCLK2
t
CRA
t
C2AD
t
OD
t
ADCLK
ADCCLK
OUTPUT
DATA
D11:D0
PGAOUT_T
t
ADC2
t
ADCLK
R(n–2)
G(n–2)
B(n–2)
R(n–1)
G(n–1)
B(n–1)
R(n)
G(n)
B(n)
R(n+1)
G(n–1)
B(n–1)
R(n)
G(n)
B(n)
R(n+1)
G(n+1)
B(n+1)
R(n+2)
PGAOUT_C
Figure 2. 3-Channel SHA Mode Timing
ANALOG
INPUTS
t
AD
t
C1
PIXEL n
PIXEL (n+1)
PIXEL (n+2)
PIXEL (n+m)
t
AD
t
C2C1
t
C1C2
CDSCLK2
t
CRB
CDSCLK1
t
C2
t
ADC2
ADCCLK
OUTPUT
DATA
D11:D0
PGAOUT_T
PIXEL (n–1)
t
C2AD
t
ADCLK
t
ADCLK
PIXEL (n–3)
t
OD
PIXEL (n–2)
PIXEL (n–1)
PIXEL (n–4)
PIXEL n
PIXEL (n+1)
PIXEL (n+2)
PGAOUT_C
Figure 3. 1-Channel CDS Mode Timing
–4–
REV. A
AD [ ANALOG DEVICES ]
