Complete 12-Bit 40 MSPS
Imaging Signal Processor
AD9821
FEATURES
Differential Sensor Input with 1 V p-p Input Range
0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Analog Preblanking Function
12-Bit 40 MSPS A/D Converter (ADC)
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 150 mW @ 3 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras Using CMOS Imagers
Industrial/Scientific Imaging
GENERAL DESCRIPTION
The AD9821 is a complete analog signal processor for imaging
applications that do not require Correlated Double Sampling
(CDS). It features a 40 MHz single-channel architecture designed
to sample and condition the outputs of CMOS imagers and CCD
arrays already containing on-chip CDS. The AD9821’s signal
chain consists of a differential input sample-and-hold amplifier
(SHA), digitally controlled variable gain amplifier (VGA), black
level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, and power-down modes.
The AD9821 operates from a single 3 V power supply, typically
dissipates 150 mW, and is packaged in a 48-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
VRT
VRB
PBLK
AD9821
0dB ~ 36dB
VIN+
VIN–
+
SHA
–
VGA
BAND GAP
REFERENCE
DRVDD
DRVSS
12
DOUT
12-BIT
ADC
BYP1
10
CLP
CLPOB
8
INTERNAL
REGISTERS
BLK CLAMP
LEVEL
DVDD
DIGITAL
INTERFACE
DVSS
SL
SCK
SDATA
DATACLK
REV. 0
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© Analog Devices, Inc., 2002
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