AD9821
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
Total Output Noise
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship 1 LSB =
(ADC Full Scale/2
N
codes) when N is the bit resolution of the ADC.
For the AD9821, 1 LSB is 500
µV.
Power Supply Rejection (PSR)
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9821 from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9821’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHA
The internal delay (also called aperture delay) is the time delay
that occurs from when the sampling edge is applied to the AD9821
until the actual sample of the input signal is held. The DATACLK
samples the input signal during the transition from low to high,
so the internal delay is measured from each clock’s rising edge
to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
DVDD
AVDD
330
60
DVSS
ACVSS
ACVSS
Figure 1. Digital Inputs— DATACLK, CLPOB, PBLK, SCK, SL
DVDD
DRVDD
Figure 3. VIN+ and VIN– (Pins 30 and 31)
DATA
DVDD
DVDD
DATA IN
THREE-
STATE
DOUT
DATA OUT
330
RNW
DVSS
DRVSS
DVSS
DVSS
DVSS
Figure 2. Data Outputs—D0–D11
Figure 4. SDATA (Pin 47)
–6–
REV. 0
AD [ ANALOG DEVICES ]
