ADM705–ADM708
PIN FUNCTION DESCRIPTION
Pin No.
ADM705
ADM706
DIP, SOIC
1
ADM707
ADM708
DIP, SPOC MicroSOIC
1
3
Mnemonic
MR
Function
Manual Reset Input. When taken below 0.8 V, a RESET is gener-
ated.
MR
can be driven from TTL, CMOS logic or from a manual
reset switch as it is internally debounced. An internal 250
µA
pull-up
current holds the input high when floating.
5 V Power Supply Input.
0 V. Ground reference for all signals.
Power-Fail Input. PFI is the noninverting input to the Power-Fail
Comparator. When PFI is less than 1.25 V,
PFO
goes low. If unused,
PFI should be connected to GND or V
CC
.
Power-Fail Output.
PFO
is the output from the Power-Fail Compara-
tor. It goes low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three-level input. If WDI remains either
high or low for longer than the watchdog timeout period, the watch-
dog output
WDO
goes low. The timer resets with each transition at
the WDI input.
Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to
a three-state buffer.
V
CC
GND
PFI
2
3
4
2
3
4
4
5
6
PFO
WDI
5
6
5
N/A
7
N/A
NC
RESET
N/A
7
6
7
8
1
No Connect.
Logic Output.
RESET
goes low for 200 ms when triggered. It can be
triggered either by V
CC
being below the reset threshold or by a low
signal on the manual reset (MR) input.
RESET
will remain low
whenever V
CC
is below the reset threshold (4.65 V in ADM705, 4.4 V
in ADM706). It remains low for 200 ms after V
CC
goes above the
reset threshold or
MR
goes from low to high. A watchdog timeout
will not trigger
RESET
unless
WDO
is connected to
MR.
Logic Output. The Watchdog Output,
WDO,
goes low if the internal
watchdog timer times out as a result of inactivity on the WDI input. It
remains low until the watchdog timer is cleared.
WDO
also goes low
during low line conditions. Whenever V
CC
is below the reset threshold,
WDO
remains low. As soon as V
CC
goes above the reset threshold,
WDO
goes high immediately.
Logic Output. RESET is an active high output suitable for systems
that use active high RESET logic. It is the inverse of
RESET.
PIN CONFIGURATION
DIP, SOIC
WDO
8
N/A
N/A
RESET
N/A
8
2
DIP, SOIC
MicroSOIC
MR
1
V
CC
2
GND 3
PFI 4
8
WDO
MR
1
V
CC
2
GND 3
PFI 4
8 RESET
RESET
1
8 NC
ADM705/
ADM706
TOP VIEW
(Not to Scale)
7
RESET
6 WDI
5
PFO
ADM707/
ADM708
TOP VIEW
(Not to Scale)
7
RESET
6 NC
5
PFO
RESET 2
ADM707/
7
PFO
MR
3
V
CC
4
ADM708
TOP VIEW
(Not to Scale)
6 PFI
5 GND
NC = NO CONNECT
NC = NO CONNECT
REV. B
–3–
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