ADV7302AKST 参数 Datasheet PDF下载

ADV7302A/ADV7303A

CLKIN_B

t

9

CONTROL

I/PS

P_HSYNC,

P_VSYNC,

P_BLANK

Cb0

Y0

t

10

PS INPUT

Cr0

Y1

Crxxx

Yxxx

Y7–Y0

t

11

t

12

t

11

t

12

CLKIN_A

CONTROL

I/PS

S_HSYNC,

S_VSYNC,

S_BLANK

S7–S0

t

9

t

10

t

12

SD INPUT

Cb0

Y0

Cr0

Y1

Cb1

Y2

t

11

Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 8-Bit (Input Mode at Subaddress 01h = 100)

P_HSYNC

P_VSYNC

a

P_BLANK

Y7–Y0

Cb

Y

Cr

Y

b

a = 32 CLKCYCLES FOR 525p

a = 24 CLKCYCLES FOR 625p

AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p

b(MIN) = 264 CLKCYCLES FOR 625p

Figure 11. PS 4:2:2 1

8-Bit Interleaved @ 54 MHz Input Timing Diagram

–10–

REV. A