Dual 5 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
Data Sheet
FEATURES
Input voltage: 4.5 V to 20 V
±1% output accuracy
Integrated 48 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 5 A/5 A
Parallel single output: 10 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductors
External compensation and soft start
Startup into precharged output
Supported by ADIsimPower
TM
design tool
TYPICAL APPLICATION CIRCUIT
R
TOP1
C
C1
C
SS1
R
C1
FB1
COMP1
SS1
EN1
PVIN1
BST1
C
IN1
V
IN
R
BOT1
INTVCC
MODE
SCFG
TRK2
TRK1
C
DRV
VDRV
GND
PGOOD2
COMP2
C
BST1
L1
SW1
M1
DL1
C
OUT1
V
OUT1
C
INT
ADP2325
PGND
M2
DL2
SW2
PVIN2
BST2
EN2
C
OUT2
L2
V
OUT2
SS2
FB2
PGOOD1
SYNC
RT
R
OSC
R
BOT2
R
TOP2
C
BST2
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
R
C2
C
C2
C
SS2
C
IN2
V
IN
10036-001
Figure 1.
GENERAL DESCRIPTION
The
is a full featured, dual output, step-down dc-to-dc
regulator based on a current mode architecture. The
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 5 A
outputs or a parallel-to-single 10 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
The switching frequency can be programmed from 250 kHz to
1.2 MHz, or it can be synchronized to an external clock to
minimize interference in multirail applications. The dual PWM
channels run 180° out of phase, thereby reducing input current
ripple as well as reducing the size of the input capacitor.
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift to provide for a stackable, multi-
phase power solution.
The
can be configured to operate in pulse frequency
modulation (PFM) mode at a light load for higher efficiency or
in forced PWM mode for noise sensitive applications. External
compensation and soft start provide design flexibility.
Independent enable inputs and power-good outputs provide
reliable power sequencing. To enhance system reliability, the device
includes undervoltage lockout (UVLO), overvoltage protection
(OVP), overcurrent protection, and thermal shutdown.
The
operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
95
90
85
EFFICIENCY (%)
V
OUT
= 5.0V
V
OUT
= 3.3V
80
75
70
65
60
55
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10036-002
50
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at V
IN
= 12 V, f
SW
= 600 kHz
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