欢迎访问ic37.com |
会员登录 免费注册
发布采购

OP16AJMDA 参数 Datasheet PDF下载

OP16AJMDA图片预览
型号: OP16AJMDA
PDF下载: 下载PDF文件 查看货源
内容描述: 精密JFET输入运算放大器 [Precision JFET-Input Operational Amplifiers]
分类和应用: 运算放大器
文件页数/大小: 12 页 / 431 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号OP16AJMDA的Datasheet PDF文件第2页浏览型号OP16AJMDA的Datasheet PDF文件第3页浏览型号OP16AJMDA的Datasheet PDF文件第4页浏览型号OP16AJMDA的Datasheet PDF文件第5页浏览型号OP16AJMDA的Datasheet PDF文件第6页浏览型号OP16AJMDA的Datasheet PDF文件第7页浏览型号OP16AJMDA的Datasheet PDF文件第8页浏览型号OP16AJMDA的Datasheet PDF文件第9页  
a
FEATURES
Significant Performance Advantages over LF155 and
LF157 Devices
Low Input Offset Voltages: 500 V Max
Low Input Offset Voltage Drift: 2.0 V/ C
Minimum Slew Rate Guaranteed on All Models
Temperature-Compensated Input Bias Currents
Bias Current Specified Warmed-Up Over Temperature
Internal Compensation
Low Input Noise Current: 0.01 pA/÷
Hz
÷
High Common-Mode Rejection Ratio: 100 dB
Models with MIL-STD 883 Processing Available
OP15
156 Speed with 155 Dissipation: 80 mW Typ
Wide Bandwidth: 6 MHz
High Slew Rate: 13 V/ s
Fast Settling to
±0.1%:
1,200 ns
OP17
Highest Slew Rate: 60 V/ s
Fastest Settling to
±0.1%:
600 ns
Highest Gain Bandwidth Product (A
VCL
= 5 Min): 30 MHz
Guaranteed Input Bias Current @ 125 C
Precision JFET-Input
Operational Amplifiers
OP15/OP17
GENERAL DESCRIPTION
The ADI-JFET input series of devices offer clear advantages over
industry-generic devices and are superior in both cost and perfor-
mance to many dielectrically-isolated and hybrid op amps. All devices
offer offset voltages as low as 0.5 mV with TCV
OS
guaranteed to
5
mV/∞C.
A unique input bias cancellation circuit reduces the I
B
by a factor 10 over conventional designs. In addition ADI specifies
I
B
and I
OS
with the devices warmed up and operating at 25∞C ambient.
These devices were designed to provide real precision performance
along with high speed. Although they can be nulled, the design
objective was to provide low offset-voltage without nulling. Systems
generally become more cost effective as the number of trim circuits
is decreased. ADI achieves this performance by use of an improved
bipolar compatible JFET process coupled with on chip, zener-zap
offset trimming.
The OP15 provides an excellent combinations of high speed and
low input offset voltage. In addition, the OP15 offers the speed
of the 156A op amp with the power dissipation of a 155A. The
combination of a low input offset voltage of 500
mV,
slew rate of
13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15
an op amp of both precision and speed. The additional features
of low supply current coupled with an input bias current makes
the OP15 ideal for a wide range of applications.
The OP17 has a slew rate of 60 V/ms and is the best choice for
applications requiring high closed-loop gain with high speed. See
OP42 datasheet for unity gain applications and the OP215 datasheet
for a dual configuration of the OP15.
V+
Q5
J5
R8*
NULL
J8
R7*
NULL
Q16
*R7,
R8 ARE ELECTRONICALLY
ADJUSTED ON CHIP FOR
MINIMUM OFFSET VOLTAGE.
Q6
R3
Q8
J11
NONINVERTING
INPUT
J1
J2
–INV
INPUT
Q1
Q3
Q12
Q7
Q9
J6
Q19
Q24
R1
Q17
R2
C2
Q2
Q4
R13
Q22
OUTPUT
Q10
J10
Q23
J9
Q11
J3
C1
7.4pF
J4
R3
R4
R5
3.6k
Q16
Q13
R6
3.6k
Q15
Q14
Q20
Q25
Q21
R11
V–
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© Analog Devices, Inc., 2002