OP191/OP291/OP491
WAFER TEST LIMITS
(@ V = +3.0 V, V
S
CM
= 0.1 V, T
A
= +25°C unless otherwise noted)
Conditions
Limit
±
300
50
8
V– to V+
70
80
50
2.8
75
350
Units
µV
max
nA max
nA
V min
dB min
dB min
V/mV min
V min
mV max
µA
max
Parameter
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
Symbol
V
OS
I
B
I
OS
V
CM
CMRR
PSRR
A
VO
V
OH
V
OL
I
SY
V
CM
= 0 V to +2.9 V
V = 2.7 V to +12 V
R
L
= 10 kΩ
R
L
= 2 kΩ to GND
R
L
= 2 kΩ to V+
V
O
= 0 V, R
L
=
∞
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .GND to V
S
+ 10 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP191/OP291/OP491G . . . . . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
14-Pin TSSOP (RU)
θ
JA2
103
158
76
120
180
θ
JC
43
43
33
36
35
Units
°C/W
°C/W
°C/W
°C/W
°C/W
Model
OP191GP
OP191GS
OP191GBC
OP291GP
OP291GS
OP291GBC
OP491GP
OP491GS
OP491HRU
OP491GBC
Temperature
Range
–40°C to +125°C
–40°C to +125°C
+25°C
–40°C to +125°C
–40°C to +125°C
+25°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
Package
Description
8-Pin Plastic DIP
8-Pin SOIC
DICE
8-Pin Plastic DIP
8-Pin SOIC
DICE
14-Pin Plastic DIP
14-Pin SOIC
14-Pin TSSOP
DICE
Package
Option
N-8
SO-8
N-8
SO-8
N-14
SO-14
RU-14
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θ
JA
is specified for the worst case conditions; i.e.,
θ
JA
is specified for device in socket
for P-DIP packages;
θ
JA
is specified for device soldered in circuit board for TSSOP
and SOIC packages.
2
1
14
13
DICE CHARACTERISTICS
3
12
1
8
7
7
4
2
11
2
6
6
3
3
5
5
10
4
4
6
7
8
9
OP191 Die Size 0.047
×
0.066 Inch,
3,102 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
Transistor Count, 74.
OP291 Die Size 0.070
×
0.070 Inch,
4,900 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
Transistor Count, 146
OP491 Die Size 0.070
×
0.110 Inch,
7,700 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
Transistor Count, 290.
REV. 0
–5–
AD [ ANALOG DEVICES ]
