Table 1A – Pin Function Table (78 Pin Plug-In)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
RT/BC
MT
STATEN
TIMEOUT
HSFAIL
DBACCEPT
SSFLAG
SVCREQ
INCMD
SSER
TESTOUT
WC1
WC3
TXINH B
T/R
CHA/CHB
CS
OE
BUSREQ
+5V
DB0(LSB)
DB2
DB4
DB6
DB8
DB10
DB12
DB14
I/O
I
I
O
O
O
I
I
I
O
I
-
O
O
O
O
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
Mode Select input - logic "1" for RT mode, logic “0” for BC mode.
Monitor mode enable. When unit is operating as a BC, a logic “0” will select
monitor mode.
Output signal in RT mode that indicates status word is being transferred on the
internal bus.
Indicates No Response Timeout has occurred during BC and RTU (RT to RT
transfer).
Output in RT mode indicating the DMA transfer did not occur in time to allow
proper operation on the 1553 bus.
Input signal used to set DBACCEPT bit in status register for response to a valid
mode command on the 1553 bus.
Input which controls the SSFLAG bit in the status register.
Input which controls the service request bit in the status word.
Output signal indicating the RT is currently in a message transfer sequence.
Input which controls the subsystem error bit in the status register.
Factory test point. Do not connect.
WC bit 1 - latched output of command word.
WC bit 3 - latched output of command word.
Transmitter inhibit output for channel B.
Output indicating T/R bit of current command word in RT mode.
Output indicating current selected channel (0 = Channel A).
Chip Select output for subsystem memory control.
Output Enable output for subsystem memory control.
Output signal used to initiate transfer to/from subsystem.
+5 Volt DC input.
Least significant bit - 16 bit parallel data bus.
Bit 2 of data bus.
Bit 4 of data bus.
Bit 6 of data bus.
Bit 8 of data bus.
Bit 10 of data bus.
Bit 12 of data bus.
Bit 14 of data bus.
Aeroflex Circuit Technology
3
SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
