ACT5270
64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5270 microprocessor
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
150, 200 MHz operating frequencies – Consult Factory for
latest speeds
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260 Dhrystone2.1 MIPS
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SPECInt95 5.0, SPECfp95 5.3
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133,
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Integrated secondary cache controller (R5000 compatible)
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Supports
512K or 2MByte block write-through secondary
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High-performance floating point unit
cycle repeat rate for common single precision operations
and some double precision operations
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Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
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Single cycle repeat rate for single precision combined multiply-
add operation
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Single
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High performance system interface compatible with RM5260,
R4600, R4700 and R5000
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64-bit
multiplexed system address/data bus for optimum price/
performance with up to 100 MHz operating frequency
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High performance write protocols maximize uncached write
bandwidth
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Supports clock divisors (2, 3, 4, 5, 6, 7, 8)
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5V compatible I/O’s
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IEEE 1149.1 JTAG boundary scan
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MIPS IV instruction set
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Floating
point multiply-add instruction increases performance in
signal processing and graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Embedded application enhancements
DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
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Specialized
Integrated on-chip caches
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16KB
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16KB
instruction - 2 way set associative
data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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Fully static CMOS design with power down logic
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Standby
reduced power mode with WAIT instruction
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6 Watts typical at 3.3V 200 MHz
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Integrated memory management unit
associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Fully
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
179-pin PGA package (Future
Product)
(P10)
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BLOCK DIAGRAM
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5270 REV 1 12/22/98
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
