Device Operation
The ACT-F128K32 MCM is composed of four, one
megabit flash EEPROMs. The following description is for
the individual flash EEPROM device, is applicable to
each of the four memory chips inside the MCM. Chip 1 is
distinguished by CE
1
and I/O
1-7
, Chip 2 by CE
2
and
I/0
8-15
, Chip 3 by CE
3
and I/0
16-23
, and Chip 4 by CE
4
and
I/0
24-31
.
Programming of the ACT-F128K32 is accomplished by
executing the program command sequence.
The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than 0.3 second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation.
During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 3 seconds (if pre-programmed). The
sector mode allows for 16K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
current consumed is typically less than 400 µA; and a
TTL standby mode (CE is held V
IH
) is approximately 1
mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (V
IL
), while CE is low and OE is at V
IH
. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
Standard
WE or CE whichever occurs first.
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Bus Operation
READ
The ACT-F128K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a command
sequence is not required to read data.
Standard
Microprocessor read cycles will retrieve array data. This
Table 2 – Sector Addresses Table
OUTPUT DISABLE
With Output-Enable at a logic high level (V
IH
), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F128K32 has two standby modes, a CMOS
standby mode (CE input held at Vcc + 0.5V), where the
Table 1 – Bus Operations
Operation
READ
STANDBY
OUTPUT DISABLE
WRITE
ENABLE SECTOR
PROTECT
VERIFY SECTOR
PROTECT
CE OE WE A0 A1 A9
L
H
L
L
L
L
L
X
H
H
V
ID
L
H
X
H
L
L
H
A
0
A
1
A
9
X
X
X
X
X
X
I/O
DOUT
HIGH Z
HIGH Z
D
IN
X
Code
A16 A15
SA0
SA1
SA2
SA3
SA4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
Address Range
00000h – 03FFFh
04000h – 07FFFh
08000h – 0BFFFh
0C000h – 0FFFFh
10000h – 13FFFh
14000h – 17FFFh
18000h – 1BFFFh
1C000h – 1FFFFh
A
0
A
1
A
9
X
L
X
H
V
ID
V
ID
SA5
SA6
SA7
Aeroflex Circuit Technology
5
SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
