Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 7).
Sector erase does not require the user to program the
device prior to erase.
The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is
not
required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.
The automatic sector erase begins after the 80µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7, Data Polling, is “1" (see Write Operatlon
Status secton) at which time the device returns to read
mode. Data Polling must be performed at an address
within any of the sectors being erased.
Figure 4 illustrates the Embedded Erase Algorithm.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = V
IL
and OE =
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Write Operation Status
D
7
DATA POLLING
The ACT-F128K8 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed.
During the program algorithm, an attempt to read the
device will produce compliment data of the data last
written to D
7
. Upon completion of the programming
algorithm an attempt to read the device will produce the
true data last written to D7. Data Polling is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence.
During the erase algorithm, D7 will be "0" until the erase
operation is completed. Upon completion data at D7 is
"1". For chip erase, the Data Polling is valid after the
rising edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is Valid
after the last rising edge of the sector erase WE pulse.
The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.
See Figures 6 and 10 for the Data Polling specifications.
Data Protection
The ACT-F128K8 is designed to offer protection against
accidental erasure or programming caused by spurious
system level singles that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the read mode. Also,
with its control register architecture, alteration of the
memory content only occurs after successful completion
of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up and
power-down transitions or system noise.
LOW V
cc
WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for V
CC
less
than 3.2V (typically 3.7V). If V
CC
< V
LKO
, the command
register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than V
LKO
. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is above
3.2V.
D
6
TOGGLE BIT
The ACT-F128K8 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms are
in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D
6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D
6
Will stop toggling
and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth
WE
pulse in the six write pulse
sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase
WE
pulse. The
Toggle Bit is active during the sector time out.
See Figure 1 and 5.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or WE
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = V
IL
, CE =
V
IH
or WE = V
IH
. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
Aeroflex Circuit Technology
7
SCD1676 REV A 5/6/98
Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
