SERIAL DATA OUT
SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
ESE OUT
START
CYCLE
ENC ENABLE
STROBE
SYNC
STROBE DATA
DON’T CARE
DATA SENT
END CYCLE
VALID SYNC
SYNC SEL
DON’T CARE
16µs
SEND DATA
(LOAD DATA)
LATCH DATA
VALID DATA
TRI-STATE DATA
DON’T CARE
DON’T CARE
DATA SELECT
DON’T CARE
FIGURE 2 – TRANSMIT MODE TIMING
SERIAL DATA IN
19
0
SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
SYNC
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
DSC OUT
START CYCLE
TAKE DATA
16µs
COMM / DATA SYNC
PREVIOUS STATE
CURRENT SYNC
TAKE DATA
STROBE DATA
END CYCLE
SERIAL DATA OUT
PREVIOUS STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNDEFINED
15
DATA SELECT
1
CURRENT DATA
TRI-STATE DATA
1
DON’T CARE
VALID WORD
2
PREVIOUS STATE
FLAG OUTPUTS
3
PREVIOUS STATE
NOT VALID
FLAGS VALID
3
BIT STATUS
4
NOT VALID
BIT STATUS VALID
4
NOTES:
1. Parallel data is held continuously in second rank receiver register, and may be enabled onto the tri-state output at any time with a LOW on DATA SELECT.
2. VALID WORD will remainLOW for 20µsec then go HIGH, if a valid sync is not received.
3. FLAG OUTPUTS are valid only when VALID WORD is LOW. Flags are MODE CODE, RT Enable, BROADCAST and VAL CMD WD.
4. BIT STATUS is valid only if wraparound transmit plus receive cycle has been performed. LATCH DATA must be HIGH, and either S/T SELECT or
RX STROBE must be HIGH for the full wraparound cycle duration.
FIGURE 3 – RECEIVE MODE TIMING
SCDCT1775 Rev B
6