BIT TIMES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COMMAND WD
SYNC
5
REMOTE TERMINAL
ADDRESS
T/R
5
SUBADDRESS
MODE
16
5
DATA WORD
COUNT/MODE CODE
1
P
DATA WORD
SYNC
STATUS WORD
SYNC
5
REMOTE TERMINAL
ADDRESS
1
1
1
P
3
RESERVED
PARITY
TERMINAL FLAG
DYNAMIC BUS
CONTROL
ACCEPTANCE
SUBSYSTEM FLAG
BUSY
BROADCAST
COMMAND RCVD
1
1
1
1
1
1
DATA
1
MESSAGE ERROR
INSTRUMENTATION
SERVICE REQUEST
Note: T/R – Transmit/Receive, P – Parity
Figure 2 – MIL-STD-1553 Word Types
RT/BC
(PIN 1)
0
1
0
MT
(PIN 2)
1
1
0
MODE
BC
RT
MT
triggers an address increment (ADRINC pin) low
output pulse used to increment the subsystem
memory address for successive transfers.
BC OPERATION
In the BC mode, the CT2565 initiates all
MIL-STD-1553 data and control message
transfers. Figure 3 details specific message
transfer flow and Table 3 lists subsystem memory
allocation. The subsystem, or host processor,
must provide a CT2565 protocol Control Word
(See Figure 4) and MIL-STD-1553 command and
data words. The CT2565 will transfer the RTU
status response and provide message transfer
validation during an active transfer. All parallel
word transfers occur in the form of a DMA
(request-grant-acknowledge) handshake with
memory read or operation as shown in Figures 5
and 6.
Command Transfer
In the BC mode pulse BCSTART (pin 41) low.
Following the pulse, the CT2565 will initiate a
DMA handshake and memory read for; the
control, word, command word(s) and up to 32
data words. No handshake timeout is enforced in
the BC mode (CT2565) remains idle during
BUSREQ to BUSGRNT), however 1553 protocol
must be maintained.
Note that commands are named from the BC's
point-of-view (for example, a TRANSMIT CMD
indicates the addressed RTU must transmit data).
Table 2 – Operating Modes
DMA - Type Handshake
All BC and RT word transfers are preceded by a
request-grant-acknowledge
format
DMA
handshake procedure. Timing information is
provided in BC, RTU and MT sections.
In MT mode, the 1553 transmission is transferred
along with an identification Word using a single
DMA handshake containing two memory-write
operations. The DMA format requires that the
subsystem provide a bus grant (BUSGRNT pin
45) low within a timeout period. Note that
BUSGRNT should be set to logic "1" before
another bus request (BUSREQ) is issued.
Memory Read/Write
With the single exception of an RT command
word transfer, all subsystem transfers take the
form of a static memory read or write. A low
pulse on both the chip select (CS) and output
enable (OE) or a low pulse on CS and write
enable (WE) (pins 17, 18 and 44 respectively)
indicates data is valid on the parallel data bus for
the duration of the pulse. The rising edge of CS
Aeroflex Circuit Technology
4
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
