One way to implement this function is to place a latching PROM
to the T0-T10 data bus. The PROM would only have to decode 11
bits (5 bits subaddress, 5 bit word count and 1 bit T/R) and have
a one bit output to place a high / low level on the NME input pin.
The upper five bits (T11-T15) are just the Remote Terminal
address for the unit which is constant so no decode of these bits is
necessary. The latching signal for the PROM would be the NVCR
line. The NME signal will remain latched and stable until the next
rising edge of NVCR.
The device will only consider a command word valid if the
following conditions are met:-
a) It contains the correct sync field.
b) Correct Manchester bi-phase (16 bits plus parity).
c) Correct parity (odd).
d) Correct terminal address or broadcast address.
e) Does not follow contiguously a valid word on the same bus.
The device will only consider a data word valid if the following
conditions are met:-
Reserved mode commands are automatically declared illegal by the
device and need not be included in the PROM decode.
a) It contains the correct sync field.
b) Correct Manchester bi-phase (16 bits plus parity).
c) Correct parity (odd).
All other conditions which require the message error bit to be set
are automatic.
d) Follows contiguously a valid word on the same bus.
Upon receipt of a valid command word the signal NVCR becomes
active low for 500 nS. (The command word is available on T0-T15
during this period for message illegalization).
1760 CHECKSUM
The 1760 checksum logic is enabled by setting the input NENCHK
active low.
On all commands except 'Wrap Around Transmit' the 32 data word
memory is cleared.
For transmit messages the checksum word is generated and
inserted in the last word position of the transmitted message.
RT TO BC TRANSFER
For received messages the last data word receive (the checksum
word) is validated. If this word meets the required criteria the
output STATUS remains low. This signal will toggle up and down
for each data word received as it is calculating the checksum.
The open drain output (STATUS) signal may be hard wired to any
of the discrete status inputs to set the required bit of the status
response in the current message. In addition it may be hard wired
to the input NILLCMD which will prevent the message being
written to memory (e.g. if it is required to set the Service Request
bit and not use the data for a failed checksum - hard wire STATUS
to NSR and NILLCMD).
If a valid command is received to transmit up to 32 data words the
device will initially respond with Status.
The signal NCMDSTRB goes low for 8.5 uS synchronized to the
1 MHZ clock indicating that a completely validated message has
been received. The transmit Command word appears on T0-T15
at this time.
If the Busy bit of the Status is set the sequence will terminate after
NCMDSTRB.
1760 HEADER WORD
The end of the NCMDSTRB will initiate the DMA cycle to transfer
the data words from the subsystem to the data buffer memory in a
single burst.
In 1760 applications the first data word received is designated the
header word. An output NHDR is provided to indicate the
presence of this word on the highway T0-T15 for verification
purposes. A failed header word may be treated in the same way as
a failed checksum.
The subsystem enables the first data word onto T0-T15 and applies
a NSSTRB to the device synchronized to the 1 MHZ clock, this
data is stored in the data buffer memory. The subsystem must
continue transferring the correct amount of words to the device in
this manner at a rate of between 62.5 kHz and 1 MHZ.
STORE RELEASED
Data is transferred from the data buffer memory to the output buffer
for transmission as required by the 1553 data bus.
The signal STREL is provided in 1760 applications to indicate to
the subsystem that the store is no longer connected to the aircraft.
If the 1760 checksum is enabled, the checksum word will be
automatically generated and transmitted as the last data word. For
example, if a Command is received to transmit five data words the
subsystem can load four or five data words. If the subsystem loads
four data words the device will generate the last data word for
transmission. If the subsystem loads five data words the device will
ignore the last data word and transmit the internally generated
checksum word instead.
INITIALISATION OF THE DEVICE
The device must be reset to a known state on power up. (The RT
address will be latched on power up). It will remain inactive until
a valid command word is received. If the device is in the process
of sequencing a command and a new command is received on the
alternative bus, the sequence will be terminated and the device will
sequence the new command.
8
SCDCT2578 REV B 3/11/98
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
