GAISLER
Features
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Dual-core SPARC V8 integer unit, each with
7-stage pipeline, 8 register windows, 4x4 KiB multi-
way instruction cache, 4x4 KiB multi-way data cache,
branch prediction, hardware multiplier and divider,
power-down mode, hardware watchpoints, single-
vector trapping, SPARC reference memory
management unit, etc.
Two high-performance double precision IEEE-754
floating point units
EDAC protected (8-bit BCH and 16-bit Reed-
Solomon) interface to multiple 8/32-bits
PROM/SRAM/SDRAM memory banks
Advanced on-chip debug support unit
192 KiB EDAC protected on-chip memory
Multiple SpaceWire links with RMAP target
Redundant 1553 BC/RT/MT interfaces
Redundant CAN 2.0 interfaces
10/100 Ethernet MAC with RMII interface
SPI, I
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C, ASCS16 (STR), SLINK interfaces
CCSDS/ECSS Telemetry and Telecommand
UARTs, Timers & Watchdog, GPIO ports,
Interrupt controllers, Status registers, JTAG, etc.
Configurable I/O switch matrix
Dual-Core LEON3-FT SPARC V8 Processor
GR712RC
Data Sheet
Description
The GR712RC is an implementation of the
dual-core LEON3FT SPARC V8 processor using
RadSafe
TM
technology. The fault tolerant design
of the processor in combination with the
radiation tolerant technology
provides total immunity
to radiation effects.
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Specification
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CQFP240 package
Total Ionizing Dose (TID) up to 300 krad(Si)
Proven Single-Event Latch-Up (SEL) immunity
Proven Single-Event Upset (SEU) tolerance
1.8V & 3.3V supply
15 mW/MHz processor core power consumption
100 MHz system frequency
200 Mbps SpaceWire links
10 Mbps CCSDS Telecommand link
50 Mbps CCSDS Telemetry link
Applications
GR712RC is an advanced system-on-chip, targeting high reliability rad-hard space,
aeronautics and military applications.
It incorporates a dual-core LEON3-FT SPARC V8 processor and is implemented
using Ramon Chips’ RadSafe
TM
library on Tower Semiconductors’ standard
180 nm CMOS technology.
Copyright Aeroflex Gaisler AB
February 2013, Issue 2.0
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
