t
WC
Address
CE
t
SCE
t
AW
t
HA
t
PWE
t
SA
t
SD
DATA VALID
R/ W
t
HD
Data in
OE
Data out
t
HZOE
HIGH IMPE DANCE
t
LZOE
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
2. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O
drivers to turn off and data to be placed on the bus for the required t
SD
.
If OE is HIGH during a R/W controlled write cycle (as in this exam-
ple), this requirement does not apply and the write pulse can be as
short as the specified t
PWE
.
3. R/W must be HIGH during all address transactions.
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)
10
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
