Table 6. Interrupt Vector Sources, Locations, and Priorities
Interrupt
Vector
Location
2012h
2010h
203Eh
203Ch
203Ah
2038h
2036h
2034h
2032h
2030h
200Eh
200Ch
PTS
Vector
Location
N/A
N/A
N/A
205Ch
205Ah
2058h
2056h
2054h
2052h
2050h
204Eh
204Ch
Priority
1
(0 is the
Lowest
Priority)
N/A
N/A
15
14
13
12
11
10
9
8
7
6
Number
Interrupt Vector
Source(s)
Special
Special
INT 15
INT 14
INT 13
INT 12
INT 11
INT 10
INT 9
INT 8
INT 7
INT 6
Unimplemented
Opcode
Software Trap
NMI
2
HSI FIFO Full
EXTINT 1
2
Timer 2 Overflow
Timer 2 Capture
2
HSI FIFO 4
Receive
Transmit
EXTINT
2
Serial Port
Unimplemented Opcode
Software Trap
NMI
HSI FIFO Full
Port 2.2
Timer 2 Overflow
Timer 2 Capture
HSI FIFO
Fourth Entry
RI Flag
3
TI Flag
3
Port 2.2 or Port 0.7
RI Flag and
TI Flag
4
Software Timer 0-3
Timer 2 Reset
HSI.0 Pin
Events on HSO.0 thru
HSO.5 Lines
HSI FIFO Full or
HSI Holding Reg.
Loaded
Single Bit Error
Single Bit Error OVF
Double Bit Error
Timer 1 or Timer 2
INT 5
INT 4
INT 3
INT 2
Software Timer
HSI.0
2
High Speed
Outputs
HSI Data Available
200Ah
2008h
2006h
2004h
204Ah
2048h
2046h
2044h
5
4
3
2
INT 1
EDAC Bit Error
2002h
2042h
1
INT 0
Timer Overflow
2000h
2040h
0
All of the previous maskable interrupts can be assigned to the PTS.
Any PTS interrupt has priority over all other maskable interrupts.
4
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
