Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY
IEEE
1394A-2000
One-Cable Transceiver/Arbiter Device
Distinguishing Features
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Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
Fully supports suspend/resume.
Supports PHY-link interface initialization and reset.
Supports 1394a-2000 register set.
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE
1394-1995
Standard
for a High Performance Serial Bus.
Fully interoperable with
FireWire
†
implementation
of
IEEE
1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Separate cable bias and driver termination voltage
supply for the port.
Meets
Intel
‡
Mobile Power Guideline 2000.
Compliant with
IEEE
Standard 1394a-2000,
IEEE
Standard for a High Performance Serial
Bus
Amendment 1.
Low power consumption during powerdown or
microlow-power sleep mode.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, will
not drive TPBIAS on the connected port even if
receiving incoming bias voltage on the port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across 1394 cable with 1394 physi-
cal layers (PHY) using 5 V supplies.
Interoperable with 1394 link-layer controllers using
5 V supplies.
1394a-2000 compliant common mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in bat-
tery-powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
— Automatic microlow-power sleep mode during
suspend.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
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Other Features
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48-pin TQFP package.
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for
analog and digital supplies and grounds.
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Features
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Provides one fully compliant cable port at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Fully supports OHCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by
concatenation.
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*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
†
FireWire
is a registered trademark of Apple Computer, Inc.
‡
Intel
is a registered trademark of Intel Corporation.
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