Data Sheet, Rev. 1
October 2002
™
FW802C Low-Power PHY
IEEE
®
1394A-2000
Two-Cable Transceiver/Arbiter Device
Distinguishing Features
s
s
s
Supports connection debounce.
Supports multispeed packet concatenation.
Supports PHY pinging and remote PHY access
packets.
Supports full suspend/resume.
Supports PHY-link interface initialization and reset.
Supports
1394
a-2000 register set.
Supports LPS/link-on as a part of PHY-link inter-
face.
Supports provisions of
IEEE 1394
-1995
Standard
for a High Performance Serial Bus
.
Fully interoperable with
FireWire
®
implementation
of
IEEE 1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Separate cable bias and driver termination voltage
supply for each port.
Meets Intel
®
Mobile Power Guideline 2000.
Compliant with
IEEE
Standard
1394a-2000,
IEEE
Standard for a High Performance Serial Bus
Amendment 1.
Low-power consumption during powerdown or
microlow-power sleep mode.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
While unpowered and connected to the bus, the
device will not drive TPBIAS on a connected port
even if receiving incoming bias voltage on that port.
Does not require external filter capacitors for PLL.
Does not require a separate 5 V supply for 5 V link
controller interoperability.
Interoperable across
1394
™
cable with
1394
physi-
cal layers (PHY) using 5 V supplies.
Interoperable with
1394
link-layer controllers using
5 V supplies.
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
1394a-2000
compliant common-mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in battery-
powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports powerdown.
— Automatic microlow-power sleep mode during
suspend.
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Other Features
s
s
s
s
48-pin TQFP package.
Single 3.3 V supply operation.
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for ana-
log and digital supplies and grounds.
s
s
Features
s
s
Provides two compliant cable ports at 100 Mbits/s,
200 Mbits/s, and 400 Mbits/s.
Supports OHCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by con-
catenation.
s
s
s
s
AGERE [ AGERE SYSTEMS ]
