Data Sheet, Rev. 1
December 2005
™
FW322 06 1394a
PCI PHY/Link Open Host Controller Interface
Features
1394a-2000 OHCI link and PHY core function in a
single device:
— Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card
designs
— Enables lower system costs
— Leverages proven 1394a-2000 PHY core design
— Demonstrated compatibility with current
Microsoft
®
Windows
®
drivers and common appli-
cations
— Demonstrated interoperability with existing, as
well as older, 1394 consumer electronics and
peripherals products
— Feature-rich implementation for high perfor-
mance in common applications
— Supports low-power system designs (CMOS
implementation, power management features)
— Provides LPS, LKON, and CNA outputs to sup-
port legacy power management implementations
OHCI:
— Complies with the 1394
OHCI 1.1 Specification
— OHCI 1.0 backwards compatible—configurable
via EEPROM to operate in either OHCI 1.0 or
OHCI 1.1 mode
— Complies with
Microsoft Windows
logo program
system and device requirements
— Listed on
Windows
hardware compatibility list
— Compatible with
Microsoft Windows
and
MacOS
®
operating systems
— 4 Kbyte isochronous transmit FIFO
— 2 Kbyte asynchronous transmit FIFO
— 4 Kbyte isochronous receive FIFO
— 2 Kbyte asynchronous receive FIFO
— Dedicated asynchronous and isochronous
descriptor-based DMA engines
— Eight isochronous transmit contexts
— Eight isochronous receive contexts
— Prefetches isochronous transmit data
— Supports posted write transactions
— Supports parallel processing of incoming phys-
ical read and write requests
— Supports notification (via interrupt) of a failed
register access
— May be used without an EEPROM when the sys-
tem BIOS is programmed with the EEPROM con-
tents.
1394a-2000 PHY core:
— Compliant with
IEEE
®
1394a-2000,
Standard for
a High Performance Serial Bus
(Supplement)
— Provides two fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic
— Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
— While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port
— Does not require external filter capacitor for PLL
— Supports link-on as a part of the internal
PHY core-link interface
— 25 MHz crystal oscillator and internal PLL
provide a 50 MHz internal link-layer controller
clock as well as transmit/receive data at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
— Interoperable across 1394 cable with 1394 phys-
ical layers (PHY core) using 5 V supplies
— Provides node power-class information signaling
for system power management
— Supports ack-accelerated arbitration and fly-by
concatenation
— Supports arbitrated short bus reset to improve
utilization of the bus
— Fully supports suspend/resume
— Supports connection debounce
— Supports multispeed packet concatenation
— Supports PHY pinging and remote PHY access
packets
— Reports cable power fail interrupt when voltage
at CPS pin falls below 7.5 V
— Provides separate cable bias and driver termina-
tion voltage supply for each port
Link:
— Cycle master and isochronous resource
manager capable
— Supports 1394a-2000 acceleration features
AGERE [ AGERE SYSTEMS ]
