USS-820FD
USB Device Controller
Data Sheet, Rev. 1
August 2004
7. Transmit isochronous behavior changed to discard
old data packets at the end of the intended frame if
not read out by a host IN (only enabled if
FEAT = 1). Data sets are not visible to the host
until the first SOF following the data set write. At
the start of a series of transfers, TXFIF will equal
00, which could allow firmware to write two data
sets during that same frame. In that case, the older
set is flushed by hardware at the first SOF.
8. Receive isochronous behavior changed to flush old
data packets at the end of the intended frame if not
read out by firmware (only enabled if FEAT = 1).
This flush decrements RXFIF and sets the
RXFLUSH register bit (RXFLG[4]), which firmware
must check before setting RXFFRC. While
RXFLUSH is set, the effect of firmware RXDAT
reads (FIFO pointer/flag changes) is blocked, to
avoid possible corruption of a new data set. If firm-
ware detects that RXFLUSH = 1, it must discard
the data set just read, since it is possibly truncated.
Firmware must still set RXFFRC in this situation,
which resets RXFLUSH to 0.
9. ASOF behavior changed to not automatically reset
when SOFODIS = 0 if FEAT = 1.
10. For nonisochronous endpoints, FFSZ = 2 indicates
8 bytes, FFSZ = 3 indicates 32 bytes (both are
interpreted as 64 bytes in the USS-820 revision B).
This will potentially allow more efficient usage of
the shared FIFO space. Only enabled if FEAT = 1.
11. USB-reset-detected condition clears the FADDR
register (if FEAT = 1). This avoids the potential
case where firmware is too slow in resetting
FADDR after USB RESET such that the host real-
locates the address to some other device and
sends traffic to that device, which is misinterpreted
by the USS-820C as intended for it. No other regis-
ter bits are cleared by USB reset.
12. USB-reset-detected condition brought out to pack-
age pin (USBR), allowing the external controller to
clear out a locked up device. Output is always 3-
stated if BDFEAT = 0. Uses pin 18 of 44-pin pack-
age, pin 19 of 48-pin package.
13. Firmware provided means to resume and reset
device if suspended. When suspended, if
SUSPP0 = 0, SUSPLOE = 0, FEAT = 1, a firmware
write of 1 to SCR bit 3 (SRESET) causes a remote
wake-up type of event (without resume signaling).
After the wake-up, when clocks are turned on, the
SRESET bit will be set and will take effect (i.e., the
USS-820C will be reset).
Appendix C. Changes from USS-820/
USS-825 Revision B to C
Note:
For Revision C, the USS-825B has been
renamed USS-820TC.
1. Hardware revision register (REV) changed from
1.0 to 1.1.
2. From the USB system and firmware points of view,
the USS-820C will appear functionally equivalent
to the USS-820B if a 1 is never written by firmware
to MCSR[3:2] or TXSTAT[6:5] (all previously
marked as reserved). The single exception is the
REV register as described above.
3. New register bits (FEAT, BDFEAT) are added to
enable new features. BDFEAT enables those fea-
tures which could impact existing boards. This
could only be an issue if NC pins were used as
connection points for other board signals. FEAT
enables all other features as indicated. FEAT is
MCSR[3]; BDFEAT is MCSR[2].
4. New FIFO status bits (RXAV/TXAV), one per FIFO,
added to indicate receive data set(s) available
(RXFIF > 00) or empty transmit data set(s) avail-
able (TXFIF < 11). If TXDSAM = 1, transmit FIFO
status bits are set if the device sends a NAK in
response to an IN packet when TXFIF = 00. The
16 register bits are formatted into two new regis-
ters (DSAV = address 1D, DSAV1 = address 1E) in
the same format as SBI/SBI1. These new read-
only bits can allow firmware to operate more effi-
ciently, because their use requires less polling
overhead. Register bits always read 0 unless FEAT
= 1 or TXDSAM = 1.
5. A logical OR of new FIFO status bits (RXAV/TXAV)
is brought out to a package pin (DSA). Package pin
is always 3-stated if BDFEAT = 0. Uses pin 15 in
44-pin package, pin 16 in 48-pin package.
6. New nonisochronous transmit mode. If enabled (by
new register bit TXNAKE = TXSTAT[5]), when the
USS-820C responds to an IN token with a NAK
because of no data sets being present (TXFIF =
00), an interrupt is generated, setting the appropri-
ate SBI/SBI1 bit. New register bit TXDSAM
(TXSTAT[6]) allows this condition to set the new
DSAV register bit and assert the new DSA output
pin (assuming they are enabled). This mode
changes the meaning of TXVOID to indicate that
such a NAK was sent, and it is the responsibility of
firmware to clear TXVOID. While TXVOID = 1, the
corresponding SBI/SBI1 register bit will remain set
as well.
54
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
