Data Sheet
June 1999
LG1600KXH Clock and Data Regenerator
For moderate damping,
ς
> 2.5
(ω
b
τ
< 0.1), the –3 dB
bandwidth of the PLL can be approximated by the loop
gain pole product:
J
BW
≈ ω
b
= K
d
R
x
K
o
while the jitter peaking can be expressed in terms of
the product of PLL bandwidth and loop filter time con-
stant:
1
1
H
(
s
)
max
≈
1
+
--------
=
1
+
------------------------
-
-
2
ω
b
τ
R
x
CK
d
K
o
As the last two expressions make clear, the PLL band-
width is controlled by the value of the external resistor
(see Figure 8), while the peaking depends both on the
resistor value (quadratically) and total loop filter capac-
itance.
Theory of Operation
(continued)
A more useful expression of the PLL characteristics is
the following
*
:
1
ω
b
1
+
-----
sτ
H
(
s
)
=
-------------------------------------
1
s
+
ω
b
1
+
-----
sτ
The jitter transfer is now directly expressed in the phys-
ical loop gain pole product,
ω
b
, and the loop filter time
constant,
τ.
Damping ratio,
ς,
and natural frequency,
ω
n
,
simply relate to these two parameters as follows:
ς
=
0.5
ω
b
τ
ω
n
⁄ τ
and
ω
n
=
* Wolaver, D.H.,
Phase-Locked Loop Circuit Design,
Prentice Hall,
1991.
1.2
3.6
10
°C
1.0
10
°C
0.8
3.0
25
°C
2.4
25
°C
J
BW
(MHz)
J
BW
(MHz)
0.6
70
°C
0.4
1.8
70
°C
1.2
0.2
0.6
0.0
0
50
100
Rx (Ω)
150
200
250
0.0
0
50
100
Rx (Ω)
150
200
250
A. LG1600KXH0622 (Cx = 0.15
µF)
B. LG1600KXH2488 (Cx = 0)
12-3231(F)r.3—12-3232(F)r.3
Figure 8. Jitter Bandwidth vs. External Resistor Value
Lucent Technologies Inc.
5
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