L9311 Full-Feature SLIC with High Longitudinal Balance,
Ringing Relay, and GR-909 Test Access
Data Sheet
July 2001
Description
(continued)
The ring trip detector requires only a single-pole filter at
the input. This will minimize the required number of
external components. To help minimize device power
dissipation, the ring trip detector is active only during
the power ring mode.
Ring trip and loop supervision status outputs appear in
a common output pin, NSTAT. NSTAT is an unlatched
supervision output; thus, an interrupt-based control
scheme may be used.
The dc current limit is set in the active modes via an
applied voltage source. The voltage source may be an
external voltage source. The voltage may be derived
via a resistor divider network from the V
REF
SLIC out-
put. A programmable external voltage source may be
used to provide software control of the loop closure
threshold. Design equations for this feature are given in
the dc Characteristics section of this data sheet. Pro-
gramming range is 10 mA to 45 mA.
Overhead is programmable in the active modes via an
applied voltage source. The voltage source may be an
external voltage source or derived via a resistor divider
network from the V
REF
SLIC output.
A programmable external voltage source may be used
to provide software control of the overhead voltage. A
potential application of this feature is to increase over-
head during test access to accommodate higher volt-
age test signals. The rate of change of the overhead
voltage may be controlled by use of a single external
capacitor at the C
F1
node. If the rate of change is
uncontrolled, there may be audible noise associated
with this transition. Design equations for this feature
are given in the dc Characteristics section of this data
sheet.
If the overhead is not programmed via a resistor, the
device develops a default overhead adequate for a
3.14 dBm overload into 900
Ω.
For the default over-
head, OVH is connected to ground.
The L9311 provides line test capability. In the test
mode, a voltage proportional to the ac or dc tip to
ground, ring to ground, tip to ring voltage or current,
may be presented at the SLIC TESTLEV output.
An ac test tone may also be applied to a test input,
TESTSIG, or through the codec RCVN/RCVP interface.
TESTSIG input is active upon entering a test state and
remains active after leaving the test mode. By varying
the frequency of the applied test tone, parameters such
as line capacitance may be measured.
TESTSIG should be externally connected to the
device’s V
REF
if it is not used during a test condition.
This may be done by a high-impedance pull-up resis-
tor. Additionally, TESTSIG should be ac coupled to the
test signal generator.
Test level outputs at TESTLEV are referenced to the
internally generated reference voltage V
REF
. This refer-
ence voltage may also be output at TESTLEV so the
users can compensate test results at TESTLEV for the
internal reference.
Note that during nontest modes, TESTLEV is high
impedance to conserve power. Input TESTSIG is
turned off during any nontest mode and during the V
REF
test mode.
The various test modes are achieved through a series
of integrated analog switches that can reconfigure the
SLIC to provide normal SLIC operation or the appropri-
ate test function. Details are given in the Special Func-
tions, Line Test section of this data sheet.
Test modes are achieved through the device state
table. When entering a test mode, the state of the SLIC
is unchanged; thus, testing can be done with the SLIC
in forward and reverse battery active modes. Addition-
ally, via the line break switches associated with the ring
relay, use of a tip open or ring open state is used to
make single-ended voltage and current measurements.
Data control is via a parallel latched data control
scheme. Data latches are edge-level sensitive. Data is
latched in when the LATCH control input goes low.
While LATCH is low, the user cannot change the data
control inputs. The data control inputs may only be
changed when LATCH is high.
Incorporation of data latches allows for data control
information and loop supervision information to be
passed to and from the SLIC via data buses rather than
on a per-line basis, thus minimizing routing complexity
and board routing area.
A device RESET pin is included. When this pin is low,
the logic inputs are overridden and the device will be
reset into SLIC forward disconnect state and the switch
into the all-off state. NSTAT is forced to the on-hook
condition when RESET is low.
The overall device protection is achieved through a
combination of an external secondary protector, along
with an integrated thermal shutdown feature, a battery
voltage window comparator, the break switch foldback
characteristic, and the dc/dynamic current-limit
response of the break and tip return switches.
6
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
