Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
F7
F5D
REG7
Q7
0
D0
DIN7
0
K7_0
K7
A
B
D1
DSEL
CE
K7_1
K7_2
CK
S/R
C
D
F6
K7_3
K6_0
REG6
Q6
DIN6
0
K6
D0
D1
A
B
C
K6_1
K6_2
DSEL
CE
1
0
CK
S/R
K6_3
D
F5MODE67
F5
K5
REG5
Q5
K5_0
K5_1
K5_2
K5_3
DIN5
0
A
B
C
D
D0
D1
DSEL
CE
CK
S/R
K4
K4_0
K4_1
K4_2
K4_3
A
B
C
D
1
0
F4
REG4
Q4
DIN4
0
D0
F5C
D1
DSEL
CE
F5MODE45
0
CK
S/R
CLK
SEL
0
0
0
CIN
CE
COUT
1
1
1
FF8
REGCOUT
D
CE
CK
ASWE
S/R
1
0
LSR
0
0
0
F3
F5B
REG3
Q3
0
D0
DIN3
0
K3_0
K3
A
B
D1
DSEL
CE
K3_1
K3_2
CK
S/R
C
D
F2
K3_3
K2_0
REG2
DIN2
0
Q2
K2
D0
D1
A
B
C
K2_1
K2_2
DSEL
CE
1
0
CK
S/R
K2_3
D
F5MODE23
F1
K1
REG1
K1_0
K1_1
K1_2
K1_3
DIN1
0
Q1
A
B
C
D
D0
D1
DSEL
CE
CK
S/R
K0
K0_0
K0_1
K0_2
K0_3
A
B
C
D
1
0
F0
REG0
DIN0
0
Q0
D0
F5A
D1
DSEL
CE
F5MODE01
0
CK
S/R
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
12
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
