OR3T30-5BA256 参数 Datasheet PDF下载

Data Sheet

June 1999

ORCA

Series 3C and 3T FPGAs

Timing Characteristics

(continued)

Clock Timing

Table 52.

ExpressCLK

(ECLK) and Fast Clock (FCLK) Timing Characteristics

OR3Cxx Commercial: V

DD

= 5.0 V ± 5%, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 5.0 V ± 10%, –40 °C

<

T

A

<

+85 °C.

OR3Txxx Commercial: V

DD

= 3.0 V to 3.6 V, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 3.0 V to 3.6 V, –40 °C

<

T

A

<

+85 °C.

Device

(T

J

= 85 °C, V

DD

= min)

Clock Control Timing Delay Through

CLKCNTRL (input from corner)

Delay Through CLKCNTRL (input from inter-

nal clock controller PAD)

Clock Shutoff Timing:

Setup from Middle ECLK (shut off to CLK)

Hold from Middle ECLK (shut off from CLK)

Setup from Corner ECLK (shut off to CLK)

Hold from Corner ECLK (shut off from CLK)

ECLK Delay (middle pad):

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

ECLK Delay (corner pad):

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

FCLK Delay (middle pad):

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

FCLK Delay (corner pad):

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

Speed

Symbol

ECLKC_DEL

ECLKM_DEL

-4

Min

0.31

1.54

Max

—

—

Min

0.31

1.17

-5

Max

—

—

Min

0.31

1.00

-6

Max

—

—

Min

0.31

0.92

-7

Max

—

—

Unit

ns

ns

OFFM_SET

OFFM_HLD

OFFC_SET

OFFC_HLD

ECLKM_DEL

0.77

0.00

0.77

0.00

—

—

—

—

—

—

—

—

—

—

—

3.50

3.67

—

—

—

5.47

5.64

—

—

—

8.24

8.87

—

—

—

10.34

11.01

—

0.51

0.00

0.51

0.00

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2.56

2.62

2.74

2.86

3.06

4.48

4.53

4.64

4.77

4.96

5.91

6.12

6.59

7.11

7.98

7.88

8.11

8.60

9.15

10.07

0.44

0.00

0.44

0.00

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2.05

2.08

2.13

2.19

2.29

3.85

3.97

4.22

4.47

4.85

4.59

4.66

4.83

5.01

5.33

6.41

6.58

6.95

7.34

7.96

0.41

0.00

0.41

0.00

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

1.78

1.80

1.85

1.90

1.98

3.36

3.47

3.69

3.92

4.27

3.81

3.89

4.06

4.26

4.59

5.40

5.58

5.94

6.33

6.94

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ECLKC_DEL

—

—

—

—

—

FCLKM_DEL

—

—

—

—

—

FCLKC_DEL

—

—

—

—

—

Notes:

The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay

includes both the input buffer delay and the clock routing to the PIC clock input.

The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer

delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

Lucent Technologies Inc.

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