Data Sheet
June 1999
ORCA
Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM Registers
The
PCM
contains eight user-programmable registers used for configuring the
PCM’s
functionality. Table 26 shows
the mapping of the registers and their functions. See Figure 46 for more information on the location of
PCM
ele-
ments that are discussed in the table. The
PCM
registers are referenced in the discussions that follow. Detailed
explanations of all register bits are supplied following the functional description of the
PCM.
Table 26. PCM Registers
Address
0
1
2
Function
Divider 0 Programming.
Programmable divider, DIV0, value and DIV0 reset bit. DIV0 can
divide the input clock to the
PCM
or can be bypassed.
Divider 1 Programming.
Programmable divider, DIV1, value and DIV1 reset bit. DIV1 can
divide the feedback clock input to the
PCM
or can be bypassed. Valid only in PLL mode.
Divider 2 Programming.
Programmable divider, DIV2, value and DIV2 reset bit. DIV2 can
divide the output of the tapped delay line or can be bypassed and is only valid for the
ExpressCLK
output.
DLL 2x Duty-Cycle Programming.
DLL mode clock doubler (2x) duty-cycle selection.
DLL 1x Duty-Cycle Programming.
Depending on the settings in other registers, this regis-
ter is for:
a. PLL mode phase/delay selection;
b. DLL mode 1x duty cycle selection; and
c. DLL mode programmable delay.
Mode Programming.
DLL/PLL mode selection, DLL 1x/2x clock selection, phase detector
feedback selection.
Clock Source Status/Output Clock Selection Programming.
Input clock selection, feed-
back clock selection,
ExpressCLK
output source selection, system clock output source selec-
tion.
PCM Control Programming.
PCM
power, reset, and configuration control.
3
4
5
6
7
Lucent Technologies Inc.
73
AGERE [ AGERE SYSTEMS ]
