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OR3T125-6PS208I 参数 Datasheet PDF下载

OR3T125-6PS208I图片预览
型号: OR3T125-6PS208I
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
PIO Register Control Signals  
Programmable Input/Output Cells  
(continued)  
As discussed in the Inputs and Outputs subsections,  
the PIO latches/FFs have various clock, clock enable  
(CE), local set/reset (LSR), and global set/reset  
(GSRN) controls. Table 11 provides a summary of  
these control signals and their effect on the PIO  
latches/FFs. Note that all control signals are optionally  
invertible.  
PIO Logic Function Generator  
The PIO logic block can also generate logic functions  
based on the signals on the OUT2 and CLK ports of  
the PIO. The functions are AND, NAND, OR, NOR,  
XOR, and XNOR. Table 10 is provided as a summary  
of the PIO logic options.  
Table 11. PIO Register Control Signals  
Table 10. PIO Logic Options  
Control Signal  
Effect/Functionality  
ExpressCLK  
Clocks input fast-capture latch;  
optionally clocks output FF, or  
3-state FF.  
Option  
Description  
OUT1OUTREG Data at OUT1 output when clock  
low, data at FF out when clock  
high.  
System Clock  
(SCLK)  
Clocks input latch/FF; optionally  
clocks output FF, or 3-state FF.  
OUT2OUTREG Data at OUT2 output when clock  
Clock Enable  
(CE)  
Optionally enables/disables input  
FF (not available for input latch  
mode); optionally enables/dis-  
ables output FF; separate CE  
inversion capability for input and  
output.  
low, data at FF out when clock  
high.  
OUT1OUT2  
Data at OUT1 output when clock  
low, data at OUT2 when clock  
high.  
AND  
NAND  
OR  
Output logical AND of signals on  
OUT2 and clock.  
Local Set/Reset Option to disable; affects input  
(LSR)  
latch/FF, output FF, and 3-state  
FF if enabled.  
Output logical NAND of signals  
on OUT2 and clock.  
Global Set/Reset Option to enable or disable per  
(GSRN) PIO after initial configuration.  
Output logical OR of signals on  
OUT2 and clock.  
Set/Reset Mode The input latch/FF, output FF, and  
3-state FF are individually set or  
reset by both the LSR and GSRN  
inputs.  
NOR  
XOR  
XNOR  
Output logical NOR of signals on  
OUT2 and clock.  
Output logical XOR of signals on  
OUT2 and clock.  
Output logical XNOR of signals  
on OUT2 and clock.  
Lucent Technologies Inc.  
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