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OR3T125-6PS208I 参数 Datasheet PDF下载

OR3T125-6PS208I图片预览
型号: OR3T125-6PS208I
PDF下载: 下载PDF文件 查看货源
内容描述: 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 210 页 / 4391 K
品牌: AGERE [ AGERE SYSTEMS ]
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Data Sheet  
June 1999  
ORCA Series 3C and 3T FPGAs  
The following occur when TS_ALL is activated:  
Special Function Blocks (continued)  
1. All of the user I/O output buffers are 3-stated, the  
user I/O input buffers are pulled up (with the pull-  
down disabled), and the input buffers are configured  
with TTL input thresholds (OR3Cxx only).  
The readback frame contains the configuration data  
and the state of the internal logic. During readback, the  
value of all registered PFU and PIC outputs can be  
captured. The following options are allowed when  
doing a capture of the PFU outputs.  
2. The TDO/RD_DATA output buffer is 3-stated.  
3. The RD_CFG, RESET, and PRGM input buffers remain  
active with a pull-up.  
1. Do not capture data (the data written to the RAMs,  
usually 0, will be read back).  
4. The DONE output buffer is 3-stated, and the input  
buffer is pulled up.  
2. Capture data upon entering readback.  
3. Capture data based upon a configurable signal  
internal to the FPGA. If this signal is tied to  
logic 0, capture RAMs are written continuously.  
Internal Oscillator  
The internal oscillator resides in the lower left corner of  
the FPGA array. It has output clock frequencies of  
1.25 MHz and 10 MHz. The internal oscillator is the  
source of the internal CCLK used for configuration. It  
may also be used after configuration as a general-  
purpose clock signal.  
4. Capture data on either options 2 or 3 above.  
The readback frame has an identical format to that of  
the configuration data frame, which is discussed later in  
the Configuration Data Format section. If LUT memory  
is not used as RAM and there is no data capture, the  
readback data (not just the format) will be identical to  
the configuration data for the same frame. This eases a  
bitwise comparison between the configuration and  
readback data. The configuration header, including the  
length count field, is not part of the readback frame.  
The readback frame contains bits in locations not used  
in the configuration. These locations need to be  
masked out when comparing the configuration and  
readback frames. The development system optionally  
provides a readback bit stream to compare to readback  
data from the FPGA. Also note that if any of the LUTs  
are used as RAM and new data is written to them,  
these bits will not have the same values as the original  
configuration data frame either.  
Global Set/Reset (GSRN)  
The GSRN logic resides in the lower right corner of the  
FPGA. GSRN is an invertible, default, active-low signal  
that is used to reset all of the user-accessible latches/  
FFs on the device. GSRN is automatically asserted at  
powerup and during configuration of the device.  
The timing of the release of GSRN at the end of config-  
uration can be programmed in the start-up logic  
described below. Following configuration, GSRN may  
be connected to the RESET pin via dedicated routing, or  
it may be connected to any signal via normal routing.  
Within each PFU and PIO, individual FFs and latches  
can be programmed to either be set or reset when  
GSRN is asserted. A new option in Series 3 allows indi-  
vidual PFUs and PIOs to turn off the GSRN signal to its  
latches/FFs after configuration.  
Global 3-State Control (TS_ALL)  
To increase the testability of the ORCA Series FPGAs,  
the global 3-state function (TS_ALL) disables the  
device. The TS_ALL signal is driven from either an  
external pin or an internal signal. Before and during  
configuration, the TS_ALL signal is driven by the input  
pad RD_CFG. After configuration, the TS_ALL signal  
can be disabled, driven from the RD_CFG input pad, or  
driven by a general routing signal in the upper right cor-  
ner. Before configuration, TS_ALL is active-low; after  
configuration, the sense of TS_ALL can be inverted.  
The RESET input pad has a special relationship to  
GSRN. During configuration, the RESET input pad  
always initiates a configuration abort, as described in  
the FPGA States of Operation section. After configura-  
tion, the global set/reset signal (GSRN) can either be  
disabled (the default), directly connected to the RESET  
input pad, or sourced by a lower-right corner signal. If  
the RESET input pad is not used as a global reset after  
configuration, this pad can be used as a normal input  
pad.  
Lucent Technologies Inc.  
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