Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
System-Level Features
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA Series 3 include:
■ Full PCI local bus compliance.
■ True, internal, 3-state, bidirectional buses with simple
■ Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC† processors with user-configurable
address space provided.
control provided by the SLIC.
■ 32 x 4 RAM per PFU, configurable as single- or dual-
port at >176 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
■ Parallel readback of configuration data capability with
* i960 is a registered trademark of Intel Corporation.
†PowerPC is a registered trademark of International Business
Machines Corporation.
the built-in microprocessor interface.
■ Programmable clock manager (PCM) adjusts clock
Table 2. ORCA Series 3 System Performance
Parameter
Speed
# PFUs
Unit
-4
78
78
-5
-6
-7
168
168
16-bit Loadable Up/Down Counter
16-bit Accumulator
2
2
102
102
131
131
MHz
MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
11.5
8
15
19
51
76
25
66
104
30
80
127
38
102
166
MHz
MHz
MHz
4
4
97
127
127
166
151
203
192
253
MHz
MHz
128 x 8 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
8
8
88
88
116
116
139
139
176
176
MHz
MHz
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs6
0.25
0
4.87
2.35
3.66
1.82
2.58
1.23
2.03
0.99
ns
ns
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs7
2
0
2
16.06 12.07 9.01
6.91 5.41 4.21
16.06 12.07 9.01
7.03
3.37
7.03
ns
ns
ns
36-bit Parity Check (internal)
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
6
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
