ORCA
Series 3C and 3T FPGAs
Data Sheet
June 1999
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
s
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the
ORCA
Series 3 include:
s
s
Full PCI local bus compliance.
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to
i960
* and
PowerPC
†
processors with user-configurable
address space provided.
Parallel readback of configuration data capability with
the built-in microprocessor interface.
Programmable clock manager (PCM) adjusts clock
True, internal, 3-state, bidirectional buses with simple
control provided by the SLIC.
32 x 4 RAM per PFU, configurable as single- or dual-
port at >176 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
s
s
s
*
i960
is a registered trademark of Intel Corporation.
†
PowerPC
is a registered trademark of International Business
Machines Corporation.
Table 2.
ORCA
Series 3 System Performance
Parameter
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
36-bit Parity Check (internal)
# PFUs
2
2
11.5
8
15
4
4
8
8
0.25
0
2
0
2
-4
78
78
19
51
76
97
127
88
88
4.87
2.35
16.06
6.91
16.06
Speed
-5
-6
102
131
102
131
25
66
104
127
166
116
116
3.66
1.82
12.07
5.41
12.07
30
80
127
151
203
139
139
2.58
1.23
9.01
4.21
9.01
-7
168
168
38
102
166
192
253
176
176
2.03
0.99
7.03
3.37
7.03
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
6
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
