ORCA
Series 3C and 3T FPGAs
Data Sheet
June 1999
Microprocessor Interface (MPI)
(continued)
Status Register
The microprocessor interface status register is a read-only register, providing information to the host processor.
Table 22. Status Register
Bit #
Bit 0
Bit 1
Reserved.
Data Ready.
Set by the
MPI,
a 1 on this bit during configuration alerts the host processor that the FPGA
is ready for another byte of configuration data. During byte-wide readback, the
MPI
sets this bit to a 1 to
tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a
host processor access (read or write) to the configuration data register.
IRQ
Pending.
The
MPI
sets this bit to 1 to indicate to the host processor that the FPGA has a pending
interrupt request. This bit may be used for the host processor to poll for interrupts if the
MPI_IRQ
pin out-
put of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is
read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to
reading this bit.
Bit Stream Error Flags.
Bits 3 and 4 are set by the
MPI
to indicate any error during FPGA configura-
tion. See bit 2 of control register 2 for the capability to alert the host processor of an error via the
IRQ
signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared
to 0 when
PRGM
goes active:
00 = No error
01 = ID error
10 = Checksum error
11 = Stop-bit/alignment error
Reserved.
INIT.
This bit reflects the binary value of the FPGA
INIT
pin.
Description
Bit 2
Bits
[4:3]
Bit 5
Bit 6
Bit 7
DONE.
This bit reflects the binary value of the FPGA DONE pin.
Configuration Data Register
The
MPI
configuration data register is a writable register in configuration mode and a readable register in readback
mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host pro-
cessor. Similarly, for readback mode, the
MPI
provides the readback data bytes in this register for the host proces-
sor.
Readback Address Register 1
The
MPI
readback address register 1 is a writable register used to accept the least significant address byte
(bits [7:0]) of the configuration data location to be read back.
Readback Address Register 2
The
MPI
readback address register 2 is a writable register used to accept the most significant address byte
(bits [15:8]) of the configuration data location to be read back.
70
Lucent Technologies Inc.
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