ORCA
Series 3C and 3T FPGAs
Data Sheet
June 1999
Programmable Logic Cells
(continued)
F7
F5D
0
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
K7
A
B
C
D
K6
A
B
C
D
K5
A
B
C
D
K4
A
B
C
D
DIN6
0
1
0
F5MODE67
REG5
D0
D1
DSEL
CE
CK
S/R
DIN7
0
REG7
D0
D1
DSEL
CE
CK
S/R
REG6
D0
D1
DSEL
CE
CK
S/R
Q7
F6
Q6
F5
DIN5
0
Q5
K5_0
K5_1
K5_2
K5_3
K4_0
K4_1
K4_2
K4_3
F5C
0
CLK
0
SEL
0
CIN
0
CE
1
1
ASWE
1
1
0
LSR
0
0
0
1
0
DIN4
0
F5MODE45
REG4
D0
D1
DSEL
CE
CK
S/R
F4
Q4
COUT
FF8
D
CE
CK
S/R
REGCOUT
F3
F5B
0
K3_0
K3_1
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
K3
A
B
C
D
K2
A
B
C
D
K1
A
B
C
D
K0
A
B
C
D
DIN2
0
1
0
F5MODE23
REG1
D0
D1
DSEL
CE
CK
S/R
DIN3
0
REG3
D0
D1
DSEL
CE
CK
S/R
REG2
D0
D1
DSEL
CE
CK
S/R
Q3
F2
Q2
F1
DIN1
0
Q1
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
0
1
0
DIN0
0
F5MODE01
REG0
D0
D1
DSEL
CE
CK
S/R
F0
Q0
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
12
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
