Data Sheet
March 2000
ORCA
®
OR3TP12 Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design imple-
mentation coupled with the high bandwidth of the
industry-standard PCI interface. The
ORCA
OR3TP12 FPSC provides a full-featured
33/50/66 MHz, 32-/64-bit PCI interface, fully
designed and tested, in hardware, plus FPGA logic
for user-programmable functions.
Table 1. PCI Local Bus Data Rates
Clock
Frequency
(MHz)
33
33
66
66
Data Path
Width (bits)
32
64
32
64
Peak Data Rate
(Mbytes)
132
264
264
528
PCI Local Bus
PCI local bus, or simply, PCI bus, has become an
industry-standard interface protocol for use in appli-
cations ranging from desktop PC busing to high-
bandwidth backplanes in networking and communi-
cations equipment. The PCI bus specification* pro-
vides for both 5 V and 3.3 V signaling environments.
The PCI interface clock speed is specified in the
range from dc to 66 MHz with detailed specifications
at 33 MHz and 66 MHz as well as recommendations
for 50 MHz operation. Data paths are defined as
either 32-bit or 64-bit. These data path and frequency
combinations allow for the peak data transfer rates
described in Table 1.
The PCI bus is electrically specified so that no glue
logic is required to interface to the bus—PCI devices
interface directly to the PCI bus. Other features
include registers for device and subsystem identifica-
tion and autoconfiguration, support for 64-bit
addressing, and multimaster capability that allows
any PCI bus Master access to any PCI bus Target.
PCI Bus Core Highlights
s
Implemented in an
ORCA
Series 3 base array, dis-
placing the bottom four rows of 18 columns.
Core is a well-tested ASIC model.
Fully compliant to Revision 2.1 of PCI Local Bus
Specification (and designed for Revision 2.2).
s
s
* PCI Local Bus Specification Rev. 2.1, PCI SIG, June 1, 1995.
Table 2.
ORCA
PCI FPSC Solutions—Available FPGA Resources
Device
OR3TP12
Usable Gates
*
30K—60K
Number of Number of Max User Max User
LUTs
Registers
RAM
I/Os
2016
2636
32K
187
Array
Size
14
×
18
Number of
PFUs
252
* The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
clk
drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32
×
4 RAM (or
512 gates) per PFU.
AGERE [ AGERE SYSTEMS ]
