Data Sheet
October 2001
ORCA
®
ORLI10G Quad 2.5 Gbits/s
10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Introduction
Agere Systems Inc. has developed a new
ORCA
Series 4 based FPSC which combines a high-speed
line interface with a flexible FPGA logic core. Built on
the Series 4 reconfigurable embedded system-on-
chips (SoC) architecture, the ORLI10G consists of an
OIF standard (OIF 99.102.5) compliant XSBI or
OIF-SFI4-01.0 SFI-4, 10 Gbits/s or 12.5 Gbits/s
transmit and 10 Gbits/s or 12.5 Gbits/s receive line
interface. Both transmit and receive interfaces con-
sist of 16-bit LVDS data up to 850 Mbits/s, integrated
transmit and receive programmable PLLs for data
rate conversions between the line-side and system-
side data rates, and a programmable logic interface
at the system end for use with SONET/SDH, Ether-
net, or OTN/digital wrapper with strong FEC system
device data standards. In addition to the embedded
functionality, the device will include up to 400k of
usable FPGA gates. The line interface includes logic
to divide the data rate down to 212 MHz or less
(1/4 line rate) or 106 MHz or less (1/8 line rate) for
transfer to the FPGA logic. The ORLI10G is designed
to connect directly to Agere’s 10 Gbits/s TTRN0110G
MUX and TRCV0110G deMUX or Agere’s
12.5 Gbits/s TTRN0126 MUX and TRCV01126
deMUX on the line side, as well as other industry-
standard devices. The programmable logic interface
on the system side allows for direct connection to a
10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH
framer/data engine, or a 10 Gbits/s/12.5 Gbits/s digi-
tal wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the
physical coding sublayer (PCS), interfaces to the
physical media attachment (PMA), and connects to
the system interface (host or switch) for the proposed
IEEE
®
802.3ae 10 Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable
device for 10G/s data solutions. It can be used as the
interface between the line interface and the system
interface in a variety of emerging networks, including
10 Gbits/s SONET/SDH (OC-192/STM-48),
10 Gbits/s optical transport networks (OTN) using
digital wrapper and strong FEC, or 10 Gbits/s Ether-
net. Other functions include use in Quad OC-48/
STM-16 SONET/SDH systems, interfaces between
Quad OC-48/STM-16 and OC-192/STM-64 compo-
nents, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is
received at the line interface and then sent to either a
4-bit or 8-bit serial-to-parallel converter. On the trans-
mit interface, either a 4-bit or 8-bit parallel-to-serial
converter is used. Thus, the data rate at the internal
FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for
great flexibility in handling clock rate conversion due
to differing amounts of overhead bits in various sys-
tem data standards. For example, the ORLI10G can
divide down the STS-192/STM-64 SONET/SDH data
line rate of 622 MHz by 4 to synchronize with a
155 MHz system clock, or the 12.5 Gbits/s Super-
FEC data line rate of 781 MHz can be divided by 8 to
98 MHz system clock or by 8 x 4/5 to provide a
78 MHz system data rate.
Table 1.
ORCA
ORLI10G—Available FPGA Logic
Device
ORLI10G
PFU
Rows
36
PFU
Columns
36
Total
PFUs
1296
User I/Os*
432
LUTs
10,368
EBR
Blocks
12
EBR Bits
(k)
111
Usable
Gates (k)
380—800
* 192 user I/Os for the 416 PBGAM package and 316 user I/Os for the 680 PBGAM package are available out of the 432 possible user
I/Os.
Note: The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate
count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU).
Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used
as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded
block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25k gates. 7k gates are used for each PLL and
50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in
the gate count calculations.
AGERE [ AGERE SYSTEMS ]
