Preliminary Data Sheet
March 2000
ORCA
®
ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
s
HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
LVDS I/Os compliant with
EIA*-644,
support hot
insertion.
8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6
UI
P-P
at 250 kHz).
Powerdown option of HSI receiver on a per-
channel basis.
Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
In-Band management and configuration.
Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
Built-in boundry scan (IEEE
†
1149.1 JTAG).
FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
s
s
s
s
s
s
s
s
s
Embedded Core Features
s
s
s
Implemented in an
ORCA
Series 3 FPGA array.
Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
s
s
s
*
EIA
is a registered trademark of Electronic Industries Associa-
tion.
†
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
ORT4622—Available FPGA Logic
Device
ORT4622
Usable
System
Gates
‡
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
259
Array Size
18 x 28
Number of
PFUs
504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
AGERE [ AGERE SYSTEMS ]
