Preliminary Data Sheet
July 2001
ORCA
®
ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s
Backplane Interface FPSC
Introduction
Agere Systems Inc. has developed a next generation
FPSC intended for high-speed serial backplane data
transmission. Built on the Series 4 reconfigurable
embedded system-on-chips (SoC) architecture, the
ORT82G5 is made up of backplane transceivers con-
taining eight channels, each operating at up to
3.125 Gbits/s (2.5 Gbits/s data rate), with a full-
duplex synchronous interface with built-in clock and
data recovery (CDR), along with up to 400k usable
FPGA system gates. The CDR circuitry is a macro-
cell available from Agere's smart silicon macro
library, and has already been implemented in numer-
ous applications including ASICs, standard products,
and FPSCs to create interfaces for SONET/SDH,
STS-48/STM-16, STS-192/STM-64, and 10 Gbit
Ethernet applications. With the addition of protocol
and access logic such as protocol-independent fram-
ers, asynchronous transfer mode (ATM) framers,
packet-over-SONET (POS) interfaces, and framers
for HDLC for Internet protocol (IP), designers can
build a configurable interface retaining proven back-
plane driver/receiver technology. Designers can also
use the device to drive high-speed data transfer
across buses within a system that are not SONET/
SDH based. For example, designers can build a 20
Gbits/s bridge for 10 Gbits/s Ethernet; the high-
speed SERDES interfaces can comprise two XAUI
interfaces with configurable back-end interfaces such
as XGMII or POS-PHY4. The ORT82G5 can also be
used to provide a full 10 Gbits/s backplane data con-
nection with protection between a line card and
switch fabric.
The ORT82G5 offers a clockless high-speed inter-
face for interdevice communication on a board or
across a backplane. The built-in clock recovery of the
ORT82G5 allows for higher system performance,
easier-to-design clock domains in a multiboard sys-
tem, and fewer signals on the backplane. Network
designers will benefit from the backplane transceiver
as a network termination device.The first version of
the device supports 8b/10b encoding/decoding and
link state machines for Ethernet, fibre-channel, and
InfiniBand™.
Version II adds SONET data scram-
bling/descrambling, streamlined SONET framing,
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Version II adds decimation and interpolation for con-
nections at 622 Mbits/s rates.
Table 1.
ORCA
ORT82G5 Family—Available FPGA Logic
Device
ORT82G5
PFU
Rows
36
PFU
Columns
36
Total
PFUs
1296
User I/O
372/432
‡
LUTs
10,368
EBR
Blocks
12
EBR Bits Usable
†
Gates (k)
(k)
111
380—800
† The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count
to a gate count assuming that 20% of the PFUs/SLICs are being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of
the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM
(EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the
embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calcula-
tions.
‡ 372 user I/Os out of a total of 432 user I/Os are bonded in the 680 PBGAM package.
AGERE [ AGERE SYSTEMS ]
