Data Sheet
August 1999
T7507 Quad PCM Codec with Filters,
Termination Impedance, and Hybrid Balance
Functional Description
(continued)
Enable Transfers when CCLK Is Not Restricted to CSEL Low
(continued)
It is recommended that a polling process be used during idle periods to ensure that a loop closure detection is rec-
ognized by the microcontroller. The maximum nominal control clock (CCLK) frequency is 2.048 MHz. Also note
that DO is 3-stated based on the state of CSEL. This allows multiple DO outputs from multiple T7507s to be tied to
a common DO bus.
Table 2. Microprocessor Interface Descriptions
Symbol
CCLK
CSEL
Description
May be gapped; Maximum frequency is 2.048 MHz.
EN
pulses are generated on rising CCLK edges.
A low-going
CSEL
initiates a write to the T7507 via the DI pin. At the same time, this initiates a read
from the T7507 on the DO pin. Data is written and read on the first eight CCLK negative transitions
after CSEL goes low. Data is applied to the T7507 operation only if CSEL is low on the eighth nega-
tive edge of CCLK. Consecutive writes are not allowed; CSEL must go high for a minimum 50 ns
between write cycles. Additionally, data is shifted from the loop status latch to the serial shift register
on the first falling CCLK pulse after CSEL goes low.
Pin for serial input data. Input data is an 8-bit word which sends control information from the micro-
controller to the T7507, L8567 SLIC, and L7583 switch. T7507 information is codec state information
and PCM time-slot assignment. L8567 and L7583 control information is passed to these components
via parallel control output pins. See Input Word Definition section for additional details.
Pin for serial data output. Output data is an 8-bit word which sends status information from T7507 par-
allel status inputs to the microcontroller via the serial data interface. Status information is received
from the T7507 via the parallel control inputs from the L8567 SLIC and L7583 switch. See Output
Word Definition section for additional details.
DI
DO
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11
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