Device Advisory
September 1999
T7633 Device Advisory for Version 1.0 of the Device
Introduction
This advisory applies to the T7633 Dual T1/E1 3.3 V Short-Haul Terminator as described in the May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
Advance Data Sheet (DS98-244TIC).
Microprocessor Timing Requirements
This section describes a modification to the microprocessor interface timing information to guarantee proper
function of the line interface clear on read status register, LIU_REG0, at address 400 and A00 (hex).
For clear on read (COR) register LIU_REG0 to clear, the chip select (CS) and address value (AD0—AD7 and
A8—A11, or A0—A11) must be active for either of the following intervals after the completion of the read (RD)
or data strobe (DS) pulse.
1. If present, two microprocessor clock (MPCK) cycles.
s
s
33 MHz maximum.
3 MHz minimum.
2. Two internal SYSCK cycles, if MPCK is not present.
s
The internal SYSCK is a clock at 16 times the line rate (24.704 MHz for DS1 or 32.768 MHz for CEPT).
Two internal SYSCK cycles, at 16 times the line rate, are equivalent to 81 ns for DS1 and 61 ns for CEPT. If
MPCK is present, this time interval can range from 61 ns to 667 ns depending upon the particular repetition
rate selected for MPCK. The microprocessor interface timing table from the T7633 advance data sheet is
shown in Table 1, Microprocessor Interface I/O Timing Specifications on page 2 with the revised timing incor-
ported in the table (notes * and †). The timing diagrams, which did not change, are shown in Figure 1—
Figure 8.
For the case where MPCK is not present, it is recommended that the hold time between the deassertion of RD
or DS and the deassertion of CS be at least 110 ns to provide a safety margin.
This requirement is not specified in the T7633 advance data sheet.
The framer portion of the terminator internally latches the decoded register address within its logic for clearing
the framer CORs, and it does not require this timing modification.
AGERE [ AGERE SYSTEMS ]
