Preliminary Data Sheet
July 2001
T8533/34 Quad Programmable Line Card
Signal Processor
Features
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General Description
The quad programmable line card signal processor
consists of four independent channels of codec and
digital signal processing functions on one chip. In
addition to the classic A-to-D and D-to-A conversion,
the device includes termination impedance synthesis
and a 64-tap echo canceller, functionally, on a per-
channel basis. The device is capable of meeting all
international standards for terminating impedance
and digital encoding format. The processing circuitry
for the adjustment of the transmit level (equalization)
to accommodate current-sensing SLICs is also
included.
The device is controlled by a serial microprocessor
interface, and a set of bidirectional I/O pins are pro-
vided, on a per-channel basis, so that this control
mechanism can be utilized to operate the battery
feed device, ringing voltage switches, etc. Common
data and clock paths can be shared over any number
of devices. All the filter coefficients, signal process-
ing, SLIC, and test features are accessible through
this interface. This serial interface can be operated at
speeds up to 4.096 Mbits/s.
The PCM bus is also programmable, with any chan-
nel capable of being assigned to any time slot.
The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in 68-pin, 64-pin, and 44-pin
surface-mount packages for economic use of board
space.
Includes codec, termination impedance, and echo
canceller in one device for line card applications
Programmable
µ-law,
linear, or A-law PCM input
and output (ITU-T G.712 compliant)
Per-channel programmable gains
Per-channel programmable internal termination
impedance
Per-channel 64-tap echo canceller (ITU-T G.168
compliant)
Fully programmable time-slot assignment
Analog and digital loopback test modes
Serial microprocessor interface
Sigma-delta converters with dither to reduce noise
Six per-channel, bidirectional control pins for SLIC
and line card function control (68-pin package)
Quad design to minimize package count on dense
line card applications
Built-in level correction (transmit equalization) to
accommodate current-sensing SLICs
Single 5 V operation
Available in 68-pin, 64-pin, and 44-pin packages
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AGERE [ AGERE SYSTEMS ]
