Product Description, Revision 4
April 29, 2005
TFRA84J13 Ultraframer
DS3/E3/DS2/E2/DS1/E1/DS0
1 Introduction
The documentation package for the TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 chip consists of the following
documents:
The
Ultramapper™
Family Register Description and the
Ultramapper
Family System Design Guide. These documents
are available on a password protected website.
The Ultraframer Product Description (this document) and the Ultraframer Hardware Design Guide. These documents
are available on the public website shown below.
To contact Agere, please see the last page of this document.
To access related documents, including the documents mentioned above, please go to the following public website, or
contact your Agere representative:
2
THSC
Framer CLK
CHI/PSB
Rx/Tx Clocks and Sync
5
MPU IF
48
MPU
FRM
x84/x63
DS1/J1/E1
5
CG
FRM PLL IF
System
Interfaces
E2AISCLK/
DS2AISCLK
1
1
(x3)
M13/E13
MUX
MRXC
DS1/J1/E1
DS2/E2
DS3/E3
21
(x3) DS3/E3
(x3) NSMI
(framer)
24
380
Shared Low Speed I/O
Miscellaneous
13
TPG/TPM
Switching modes:
8PSB
(x16)- x84/X63 DS1/J1/E1
x2016 DS0/E0
4CHI
(x18) - x2016 DS0/E0
x84/x63
DS1/E1
JTAG
DJA
Transport modes:
4DS1/J1/E1
(x86) -x84/x63 + prot
.
4DS2/E2
(X86) – x63/x36 + prot.
2
JTAG IF
5
DS1XCLK,
E1XCLK
Power and GND pins not shown
10/10/02
Figure 1-1. Ultraframer Block Diagram and High-Level Interface Definition
AGERE [ AGERE SYSTEMS ]
