Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features
s
1.2 STS/STM Pointer Interpreter
s
s
Versatile IC supports 155/51 Mbits/s SONET/SDH
interface solutions for T3/E3, DS2, T1/E1/J1, and
DS0/E0/J0 applications.
Implementation supports both linear (1 + 1, unpro-
tected) and ring (UPSR) network topologies.
Provides full termination of up to 21 E1, 28 T1, or
28 J1.
Low power 3.3 V supply.
–40
°C
to +85 °C industrial temperature range.
456-pin ball grid array (PBGA) package.
Complies with
Bellcore*,
ITU,
ANSI
†
, ETSI and Jap-
anese TTC standards: GR-253-CORE, GR-499,
(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,
G.962, G.964, G.965, Q.542, T1.105, JT-G704,
JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,
ETS 300 011, T1.107, T1.404.
Interprets STS/AU/TU-3 pointers.
Synchronizes 8 kHz frame and 2 kHz superframe to
system/shelf timing reference by setting the transmit
STS-3/STM-1 pointers to a fixed value of 522.
Monitors/terminates SPE path overhead.
s
s
s
1.3 Telecom Bus Interface
s
s
s
s
s
Telecom bus interface to mate devices including
clock, data[8], parity, SPE-, J0-, J1-, and V1 timing
indicator.
Line and path RDI and REI signals passed to mate
devices.
Three Super Mapper devices, two configured as
mate devices, provide full termination of an
STS-3/STM-1. A three-chip solution to terminate
84 DS1s/J1s or 63 E1s.
s
s
1.1 SONET/SDH Interface
1.4 VT Termination/Generation (x28/x21)
s
Termination of a single 155 Mbits/s STS-3/STM-1 or
single 51 Mbits/s STS-1/STM-0.
Built-in clock and data recovery circuit at
155 Mbits/s STS-3/STM-1 interface (can be dese-
lected if external clock recovery is provided).
Supports overhead processing for all transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel. Con-
figurable as dedicated DCC channels.
Software controlled linear 1 + 1 protection via dedi-
cated interface to protection card.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm report-
ing.
Built-in diagnostic loopback modes.
8 kHz line frame sync output.
s
s
Monitors/terminates VT path overhead for
28 VT1.5/TU-11 or 21 VT2/TU-12.
Synchronizes VT/TU SPE to system/shelf timing ref-
erence by setting the transmit VT/TU pointers to fixed
values for asynchronous mapping or by dynamically
changing the transmit VT/TU pointers for byte syn-
chronous mapping.
Fixed pointer generation in transmit side for asyn-
chronous mapping.
Dynamic pointer generation in transmit side for byte-
synchronous mapping.
s
s
s
s
s
s
s
s
1.5 Mapping/Multiplexing Modes (x28/x21)
s
s
s
Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
Maps T1/E1/J1 into VT/TU (including DS1 into
TU-12).
Supports asynchronous, byte-synchronous, and bit-
synchronous mapping.
s
*
Bellcore
is now
Telcordia Technologies. Telcordia Technologies
is a
trademark of Telcordia Technologies, Inc.
†
ANSI
is a registered trademark of American National Standards
Institute, Inc.
s
AGERE [ AGERE SYSTEMS ]
