Preliminary Data Sheet
August 2000
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Demultiplexer Operation
The serial 2.5 Gbits/s data is clocked into a 1:16 demultiplexer by the recovered 2.5 GHz clock. The demultiplexed
parallel data is retimed with a 155 MHz clock that is derived from the recovered clock. The relationship between
the serial input data and the parallel D[15:0] bits is given in Figure 8. D15 is the bit that was received first in time in
the serial input data stream.
D15
(MSB)
D14
D1
D0
(LSB)
(D0 RECEIVED LAST)
D15
(D15 RECEIVED FIRST)
TIME
5-8063(F).a
Figure 8. Serial Input to Parallel Output Data Relationship
Parity Generation (PARITYP/N)
The parity pin (PARITYP/N) is a logic 0 when the number of 1s in the 16-bit output register is an even number, and
the parity pin is a logic 1 when the number of 1s in the output register is an odd number.
Demultiplexer Powerdown (PDDMXN)
The entire demultiplexer and parity generator functionality can be powered down for systems requiring only the
2.5 GHz clock and data outputs. Setting PDDMXN = 0 powers down the demultiplexer and parity generation func-
tions as well as the CK155P/N output clock signal. When PDDMXN = 0, the D[15:0] and PARITYP/N pins should
be left unconnected.
Demultiplexer Data Mute (MUTEDMXN)
Setting the MUTEDMXN = 0 mutes the data going into the demultiplexer and forces all zeros to appear at the par-
allel outputs (D[15:0]).
CK155P/N Low-Speed Output Mute (MUTE155N)
The 155 MHz low-speed clock output (CK155P, CK155N) can be forced to logic low by setting MUTE155N, which
is an active-low CMOS input with an internal pull-up resistor. A ground or logic low applied to MUTE155N mutes
the CK155P/N output.
Lucent Technologies Inc.
17
AGERE [ AGERE SYSTEMS ]
