Data Sheet, Revision 3
September 21, 2005
TSI-1
1k x 1k Time-Slot Interchanger
1 Introduction
The last issue of this data sheet was August 31, 2005. A change history is included in Section
Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text
are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or
grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically
mentioned.
This document consists of two major sections:
The
TSI-1
device hardware description. This section contains ball information, operating conditions, dc electrical charac-
teristics, timing diagrams, ac characteristics, and packaging information.
The
TSI-1
device register description. This section contains register information.
1.1 Related Documents
The documentation package for this device consists of the following documents:
The TSI-1 1k x 1k Time-Slot Interchanger Product Brief, the TSI Family Selection Guide, the TSI-1 1k x 1k Time-Slot
Interchanger Data Sheet (this document), and the TSI-1 Time-Slot Interchanger System Design Guide.
These documents are available on the public website shown below.
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To access related documents, including the documents mentioned above, please go to the following public website, or con-
tact your Agere representative (see the last page of this document).
1.2 Block Diagram and High-Level Interface Definition
TEST ACCESS
PORT
TEST PATTERN
MONITOR
TEST PATTERN
GENERATOR
1k x 1k Switch Fabric
16
RECEIVE
CHI
DATA
STORE
TRANSMIT
CHI
16
WRITE ADDRESS
COUNTER
CLOCK
GENERATOR
CONNECTION
STORE
READ ADDRESS
COUNTER
MICROPROCESSOR
INTERFACE
Figure 1-1. Block Diagram and High-Level Interface Definition
AGERE [ AGERE SYSTEMS ]
