Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Thermal Characteristics
The TTSV02622 is a 5.86 mm x 6.49 mm die in the 272-pin PBGA (2-layer BGA). For thermal characteristics, the
following values should be used:
s
s
s
s
Θ
Jc = 15.38 °C/W
Θ
Jb = 25.09 °C/W
Θ
Ja = 31.92 °C/W
ΨJt
= 1.00 °C/W
Table 11. Thermal Resistance—Junction to Ambient
Air Speed in Linear Feet per Minute (LFPM)
JEDEC Standard Natural Convection
200
500
Θ
Ja (°C/W)
29.48
28.65
27.42
Power Consumption (Advance)
Table 12. Power Consumption (Advance)
Parameter
2 Channel
Condition
At 3.3 V
At 3.465 V
Max
1.6
1.7
Unit
W
W
Electrical Characteristics
Table 13. LVTTL Electrical Characteristics
Parameter
Output Voltage:
Low
High
Symbol
V
OL
V
OH
Test Conditions
—
—
Min
—
2.4
Max
0.4
—
Unit
V
V
Propagation Delay Specifications
1. Delay in 77.78 MHz system clocks from the Tx line input to the LVDS backplane output is seven clocks (see
2. Propagation delay from a change on the PROT SW pin to a protection switch activity:
s
NORM to HI-Z:
— Five rising edges of SYS_CLK from assertion of the PROT_SW_A/C pins to the data changing to HI-Z.
NORM to MUX switch:
— Eight rising edges of SYS_CLK from assertion of the PROT_SW_A/C pins to the data changing from stream
A to B. (See Figure 17 on page 58.)
s
3. Propagation delay from A1 STS-1 #1 arriving at LVDS input to RX_TOH_FP is 56 SYS_CLKs, and
six TOH_CLKs. This will vary by ±14 SYS_CLKs, 12 each way for the FIFO alignment, and ±2 SYS_CLKs due
to the variability in the clock recovery of the CDR macro.
4. Delay from CS_N going active (CPU write access to reset the chip) to reset being deactivated and CPU inter-
face being ready to handle another access is nine SYS_CLKs.
Agere Systems Inc.
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