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HCPL-2211 参数 Datasheet PDF下载

HCPL-2211图片预览
型号: HCPL-2211
PDF下载: 下载PDF文件 查看货源
内容描述: 非常高CMR ,宽VCC逻辑门光电耦合器 [Very High CMR, Wide VCC Logic Gate Optocouplers]
分类和应用: 光电
文件页数/大小: 16 页 / 239 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Package Characteristics
Parameter
Input-Output Momentary
Withstand
HCNW22XX
*
Voltage
Input-Output Resistance
HCNW22XX
Input-Output Capacitance
HCNW22XX
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
Sym.
V
ISO
Min. Typ. Max. Units
Test Conditions
2500
V rms RH < 50%, t = 1 min.
5000
T
A
= 25°C
10
12
10
13
0.6
0.5
0.005
10
11
0.25
T
A
= 25°C
T
A
= 100°C
pF
0.6
µA
pF
T
A
= 25°C
Relative Humidity = 45%,
t = 5 s, V
I-I
= 500 V
V
I-I
= 500 V
f = 1 MHz
f = 1 MHz,
V
I-O
= 0 Vdc
5
12
12
12
V
I-O
= 500 Vdc
Fig. Note
5, 10
5, 11
5
R
I-O
10
12
10
11
C
I-O
I
I-I
R
I-I
C
I-I
*The
Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,”
publication number 5963-2203E.
Notes:
1. Each channel.
2. Derate total package power dissipation, P
T
, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
3. Duration of output short circuit time should not exceed 10 ms.
4. For single devices, input capacitance is measured between pin 2 and pin 3.
5. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
6. The t
PLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the
leading edge of the output pulse. The t
PHL
propagation delay is measured from the 50% point on the trailing edge of the input
pulse to the 1.3 V point on the trailing edge of the output pulse.
7. CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state,
V
O
> 2.0 V. CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic
low state, V
O
< 0.8 V.
8. For HCPL-2202/12, V
O
is on pin 6.
9. Use of a 0.1
µF
bypass capacitor connected between pins 5 and 8 is recommended.
10. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V rms for one second
(leakage detection current limit, I
I-O
5
µA).
This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
6000 V rms for one second
(leakage detection current limit, I
I-O
5
µA).
This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table.
12. For HCPL-2231/32 only. Measured between pins 1 and 2, shorted together, and pins 3 and 4, shorted together.
1-141