path using the -EQEN pin, # 32.
Setting pin #32 high disables the
equalizer. Setting pin # 32 low
enables the equalizer. The typical
performance of the input
equalizer is shown in the
(frequency response) plot of
Figure 7. The impact of the
equalizer is improved BER
performance over long lengths of
cable (10 to 20 meters).
Connected to the
±
DI input pins,
prior to the equalizer, are the loss
of light detectors, LOLA (pin 28)
and LOLB (pin 29). Actually,
since these detectors monitor the
incoming serial electrical data
stream, they can be thought of as
loss of “signal” detectors. These
signals can be used to determine
if the incoming signal line is
connected properly. In the case
of a fiber optic system they can
be used to shut down laser output
power for laser safety considera-
tions. The LOL detectors measure
transitions in the incoming data
stream that exceed a pre-set
peak-to-peak differential signal or
threshold level. The default peak-
to-peak differential threshold
voltage is 25 mV and can be
adjusted by connecting a resistive
divider to the DR_REF pin (#21)
as shown in Figure 6. The rela-
tionship of the DR_REF voltage
to the peak-to-peak differential
threshold voltage is shown in
Figure 8. When the input signal
level falls below the threshold
voltage for 4 clock cycles, or 80
bit times, the signals at pins 28
and 29 will go high.
Once the serial data stream
passes the cable equalizer
function it is directed to an Input
Select section. A second high
speed serial data input, denoted
±
LIN, is applied at pins # 16 and
# 17 and is connected directly to
the Input Select section. This data
input is intended for diagnostic
purposes. It is not affected by the
cable equalizer and has no effect
on the loss of light detectors. The
±
LIN input should mainly be
used when it is desired to directly
connect the local transmitter
serial output data stream to the
local receiver (local loopback).
The Input Select function uses
the EWRAP signal, pin # 34, to
determine which serial data
stream to pass on to the rest of
the receiver. If EWRAP is high,
then the
±
LIN signal is used. If
EWRAP is low the
±
DI signal is
used.
The PLL and Clock select
circuitry contains a monolithic,
tunable, oscillator. This oscillator
phase locks to the selected high
speed data input and recovers the
high speed serial clock. To keep
the internal oscillator tuned close
to the incoming signal frequency,
an external reference oscillator is
applied to the CLKIN input, pin
# 7. The signal on the -LCK_REF
input, pin # 36, controls whether
the receiver oscillator locks to the
reference oscillator or to the
+5 V
2 KΩ
8 KΩ POTENTIOMETER
PIN #21,
DR_REF
2 KΩ
incoming data stream. When
-LCK_REF is toggled low, the
receiver frequency locks to the
signal at CLKIN. When the
-LCK_REF pin is toggled high,
the receiver phase locks to the
selected high speed serial data
input. This process of locking to
a local reference oscillator, prior
to receiving incoming data,
improves (shortens) the overall
time required by the receiver to
acquire lock. The LUNUSE input,
pin 73 will cause the receiver to
frequency lock on the CLKIN
signal under faulty or no input
signal conditions. The LUNUSE
signal needs to be provided to the
receiver by an external open fiber
control circuit or other control
logic. Once the receiver has
locked to the incoming data
stream at
±
DI (EWRAP = 0 and
-LCKREF = 1), if LUNUSE
toggles high then the receiver will
switch to frequency lock on
CLKIN. If, however, the receiver
is locked onto the local data
wrapped back to the
±
LI input
(EWRAP = 1 and -LCKREF = 1)
then the receiver stays locked to
the incoming signal at
±
LI even
when LUNUSE goes high. In
summary, when the LUNUSE
input is set low, the receiver
frequency locks to the CLKIN
signal when the input to
-LCKREF is low and phase locks
to either the
±
DI or
±
LI signal,
depending on which input is
selected, when -LCKREF toggles
high. LUNUSE then, is used to
cause the receiver to frequency
lock to the reference oscillator at
CLKIN after the receiver has
established phase lock to the
incoming data signal at
±
DI, and
the system determines the link is
faulty and not in EWRAP mode.
Figure 6. Simple Circuit Used to
Adjust the Voltage on Rx pin # 21,
DR_REF.
661
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
