HDMP-1685A Timing Characteristics – Receiver Sections – Rising Edge Clocking
T
A
= 0°C to T
C
= 85°C, V
CC
= 3.15 V to 3.45 V
Symbol
f_lock
B_sync
[1,2]
t
RXS
t
RXH
Parameter
Frequency Lock at Powerup
Bit Sync Time
RX [0:3][0:4] Setup Time (Data Valid Before Clock)
RX [0:3][0:4] Hold Time (Data Valid After Clock)
RC [0:3][1] to RC [0:3][0] Skew
RC [0:3][1] and RC [0:3][0] Duty Cycle
t_rxlat
[3]
Receiver Latency
Units
µs
bits
ps
ps
ns
%
ns
bits
1200
800
3.5
40
16
20
4.5
60
Min.
Typ.
Max.
500
2500
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]).
8 ns
RC[0:3][1]
RC[0:3][0]
RXS
RXH
RXS
RXH
RX[0:3][0:4]
Figure 5a. Receiver section parallel output timing using rising edge of both RC[0:3][0] and RC[0:3][1].
6
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